Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.

Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.

Abstract: A semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. The conductive line and the conductive via are disposed in the single-layered dielectric layer. The conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.

Abstract: A motor drive system includes an electric motor, a drive circuit and a control unit. The drive circuit provides a driving current to the electric motor. A current command generator of the control unit generates a current command according to a torque command and a motor operating information. The driving current is converted into a d-axis current and/or a q-axis current by the control unit. Consequently, the driving current is close to the d-axis current command and/or the q-axis current command corresponding to the current command. If a value of the torque command is positive, the current command generator generates the corresponding current command according to a MTPA lookup table. If the value of the torque command is negative, the current command generator generates the corresponding current command according to a zero recycle lookup table.

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: In one example, an electronic device housing may include a substrate, an insulating adhesive layer formed on a surface of the substrate, a patterned electroless plating layer formed on the insulating adhesive layer, and a patterned electrolytic plating layer formed on the patterned electroless plating layer.

Abstract: Provided are a memory device and an operation method thereof. The memory device includes a plurality of word lines. The operation method comprising: performing a pre-fill operation on the word lines, in a first loop, applying a selected word line voltage on a first selected word line group and applying an unselected word line voltage on a first unselected word line group, and in a second loop, applying the selected word line voltage on a second selected word line group and applying the unselected word line voltage on a second unselected word line group, the first selected word line group being different from the second selected word line group, and the first unselected word line group being different from the second unselected word line group; performing an erase operation on the word lines; and performing a programming operation on the word lines.

Abstract: In one example, an electronic device housing may include a substrate, an insulating adhesive layer formed on a surface of the substrate, a patterned electroless plating layer formed on the insulating adhesive layer, and a patterned electrolytic plating layer formed on the patterned electroless plating layer.

Abstract: Examples of body panels with connectors are described herein. In an example, a body panel of a portable electronic device may include a connector affixed thereto, in an assembled state of the body panel on the portable electronic device, the connector may be positioned between a battery and a motherboard of the portable electronic device. The connector may electrically couple the battery with the motherboard, in the assembled state.

Abstract: A memory device includes: a first bit line located on a dielectric layer and a second bit line located over the dielectric layer; a first word line and a second word line located between the first bit line and the second bit line; a source line located between the first word line and the second word line; a channel pillar penetrating through the first word line and the source line and the second word line, and being connected to the first bit line, the source line and the second bit line; and a charge storage structure including an upper portion surrounding an upper sidewall of the channel pillar and located between the second word line and the channel pillar; and a lower portion surrounding a lower sidewall of the channel pillar and located between the first word line and the channel pillar.

Abstract: A memory device includes: a first bit line located on a dielectric layer and a second bit line located over the dielectric layer; a first word line and a second word line located between the first bit line and the second bit line; a source line located between the first word line and the second word line; a channel pillar penetrating through the first word line and the source line and the second word line, and being connected to the first bit line, the source line and the second bit line; and a charge storage structure including an upper portion surrounding an upper sidewall of the channel pillar and located between the second word line and the channel pillar; and a lower portion surrounding a lower sidewall of the channel pillar and located between the first word line and the channel pillar.

Abstract: A memory device and a programming method thereof are provided. The memory device includes a memory array, a plurality of word lines and a voltage generator. During a programming procedure, one of the word lines is at a selected state and others of the word lines are at a deselected state. Some of the word lines, which are at the deselected state, are classified into a first group and a second group. The first group and the second group are respectively located at two sides of the word line, which is at the selected state. The voltage generator provides a programming voltage to the word line, which is at the select state, during a programming duration. The voltage generator provides a first two-stage voltage waveform to the word lines in the first group and provides a second two-stage voltage waveform to the word lines in the second group.

Abstract: Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.

Abstract: A memory device includes a substrate, a stacked structure, a plurality of channel structures, a plurality of memory layers, and a plurality of shallow isolation structures. The substrate has an upper surface. The stacked structure is disposed on an upper surface of the substrate, wherein the stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternatively stacked on the upper surface. The channel structures penetrate portions of the stacked structure and are electrically connected to the substrate. The memory layers surround the corresponding ones of the channel structures. The shallow isolation structures extend from a top surface of the stacked structure toward the substrate, wherein each of the shallow isolation structures includes a substance having a dielectric constant of less than 3.9.

Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour.

Abstract: A computer program product enables an advertisement audience dynamical detection circuit to conduct an advertisement audience quantity detecting operation. The advertisement audience quantity detecting operation includes: receiving a probe request frame transmitted from other wireless communication device; recording the arrival time of the probe request frame; inspecting the frame field configuration of the probe request frame; allocating the probe request to a corresponding data group according to the arrival time and frame field configuration of the probe request frame and a sequence control value in the header of the probe request frame while ensuring all probe request frames in the same data group have same frame field configuration; and calculating an estimated quantity of advertisement audiences passing through a specific location in a specific time period based on a total quantity of resulting data groups.

Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.

Abstract: A single-magnet double-tone-circuit coaxial loudspeaker includes a shell, a U iron, a magnet, a spring washer, a first diaphragm assembly, a second diaphragm assembly, an upper cover and a terminal plate. A single “magnet+spring washer+U iron” magnetic circuit is extended to be two upper-lower coaxial magnetic circuits, therefore, the first diaphragm assembly and the second diaphragm assembly which are electrically connected to the terminal plate generate a double-magnetic-circuit feature by sharing a single-magnet system. High frequency and low frequency wave bands are driven independently, such that high frequency and low frequency portions can achieve a better sound resolution effect. The complementation of the two reduces distortion, thus improves the overall acoustic performance of the loudspeaker.

Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.

Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.