Abstract: A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.

Abstract: A unit for opening an insert of a test tray which comprises an accommodating space for accommodating a semiconductor device and a support for supporting the semiconductor device accommodated in the accommodating space, the unit includes a body, a pair of opening devices provided in the body to open the insert, and a positioning guide unit protruding to be inserted into an accommodating space for a semiconductor device when opening the insert and supporting the semiconductor device that is transferred into the accommodating space to be spaced upward apart from a support provided in the accommodating space.

Abstract: A system to support the testing of electronic devices and a temperature control unit for the system are disclosed. A temperature controlling method for a chamber of the system is also disclosed. Low or high temperature air is supplied to the inside of the chamber when the electronic devices are tested at low or high temperature. External air is supplied to the inside of the chamber when the electronic devices are tested at room temperature.

Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

Abstract: A test handler is disclosed in the present invention. The test handler may include a test tray on which a plurality of inserts are arrayed for loading at least one semiconductor device, at least one opening unit for simultaneously opening one part of the plurality of inserts which are arrayed on one part of the test tray, and a test tray transfer apparatus for allowing the opening unit to simultaneously open other parts of the plurality of inserts which are arrayed on another part of the test tray as the test tray is transferred. Therefore, although semiconductor devices to be tested change their sizes, the replaced parts of the test handler are reduced in number, thereby reducing manufacturing cost and replacement work time. The inventive test handler reduces semiconductor devices loading time, reduces jamming, increases teaching efficiency and improves space utilization efficiency. Furthermore, the test handler can be applied to various types of testers.

Abstract: The present invention relates to a test tray for a test handler. According to this invention, there is disclosed a technique that an insert loaded in a loading part which is arranged in a matrix pattern in a frame of the test tray allows an amount and direction of free movement thereof to be determined in accordance with a location of the loading part, where the insert is loaded, on the matrix, thereby enabling a thermal expansion or contraction of a match plate or the test tray to be compensated.

Abstract: A test handler is disclosed in the present invention. The test handler may include a test tray on which a plurality of inserts are arrayed for loading at least one semiconductor device, at least one opening unit for simultaneously opening one part of the plurality of inserts which are arrayed on one part of the test tray, and a test tray transfer apparatus for allowing the opening unit to simultaneously open other parts of the plurality of inserts which are arrayed on another part of the test tray as the test tray is transferred. Therefore, although semiconductor devices to be tested change their sizes, the replaced parts of the test handler are reduced in number, thereby reducing manufacturing cost and replacement work time. The inventive test handler reduces semiconductor devices loading time, reduces jamming, increases teaching efficiency and improves space utilization efficiency. Furthermore, the test handler can be applied to various types of testers.

Abstract: A test handler is disclosed. A posture changing unit for changing a posture of a test tray on which semiconductor devices have been loaded changes the posture of the test tray in a soak chamber. While the posture of the test tray is changed, the devices can be pre-heated/pre-cooled, thereby reducing the soak chamber length and the pre-heating/pre-cooling time.

Abstract: A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.

Abstract: A test handler is disclosed, which comprises a test tray, at least one opening unit, and a position changing apparatus. The test tray aligns a plurality of inserts on its side. Each insert loads at least one semiconductor device thereon. The opening unit opens inserts at one part of the one side of the test tray. The position changing apparatus moves at least one opening unit in such a way that the at least one opening units can be located at another part of the one side of the test tray, such that the at least one opening units can open inserts at said another part of the one side of the test tray. The present invention can reduce the number of replaced parts according to change in the semiconductor device size, production cost, and part replacement time. Also, the present invention can be easily applied to various types of testers.

Abstract: A pick and place apparatus includes a 1st to an nth device holding element arranged in a lengthwise direction, every one of the 1st to the nth device holding element being connected to its neighboring one(s) of the 1st to the nth device holding element by means of at least one pitch setting ring; a belt having a first coupling part at an upper part thereof for being coupled to the 1st device holding element and a second coupling part at a lower part thereof for being coupled to the nth device holding element; and a driven pulley and a differential pulley. The driven and the differential pulley are rotated by being engaged with the belt to move the 1st and the nth device holding element such that the 1st device holding element moves in a direction opposite to the nth device holding element.

Abstract: The present invention relates to a test tray for a test handler. According to this invention, there is disclosed a technique that an insert loaded in a loading part which is arranged in a matrix pattern in a frame of the test tray allows an amount and direction of free movement thereof to be determined in accordance with a location of the loading part, where the insert is loaded, on the matrix, thereby enabling a thermal expansion or contraction of a match plate or the test tray to be compensated.

Abstract: A test handler includes a loading unit for loading semiconductor devices from customer trays onto a test tray; a test chamber for performing a test for the semiconductor devices loaded on the test tray; a pushing unit having at least one pushing member for pushing the test tray located in the test chamber to be tested, and a press unit for operating the pushing member; a position control unit for adjusting a position of the pushing member to compensate a deviation between the pushing member and the test tray due to a thermal expansion or contraction of any one of the pushing member and the test tray; and an unloading unit for unloading the semiconductor devices loaded on the test tray onto the customer trays after a test for the semiconductor devices is completed.

Abstract: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.

Abstract: A pick and place apparatus includes a plurality of device holing elements in a predetermined arrangement; a power supply mechanism for supplying a power for controlling a horizontal pitch between the plurality of device holding elements; a power transmission mechanism for delivering the power from the power supply mechanism to the plurality of device holding elements as a translational force in a horizontal direction; a first linear motion guide mechanism for guiding horizontal movements of some of the plurality of device holding elements; and a second linear motion guide mechanism disposed below the first linear motion guide mechanism, for guiding horizontal movements of the other device holding elements. The plurality of device holding elements are slidably coupled to the first and the second linear motion guide mechanism alternately.

Abstract: A test handler is disclosed. First and second gripping blocks for respective front and rear test trays to be transferred along a circulation path move together in a circulation direction, but move independently in a direction perpendicular to the circulation path and grip and release independently. The test trays can be transferred by a single power source and interference between an assisting a test and a transferring can be minimized.

Abstract: A test handler is disclosed. The test handler includes first to third transfers for transferring a user tray, and first to third horizontal movement units suitable for respectively moving the first to third transfers in the horizontal direction. The first to third horizontal movement units are independently operated such that each of the first to third transfers can perform independently horizontal movements. Each of the first to third transfers performs based on its previously allocated function, thereby enhancing test process speed for devices.

Abstract: A clamping apparatus for clamping a plurality of Hi-Fix boards arranged in a row, includes at least one rotational clamping unit installed to clamp facing end sides of the two or more Hi-Fix boards together, and a plurality of clamping units installed to clamp end sides of the Hi-Fix boards other than the facing sides thereof. The rotational clamping unit includes a clamper installed to rotate about a fixed rotation point to clamp or release the claming of the facing end sides of the two or more Hi-Fix boards, and a driving unit for providing a rotational force to the clamper.

Abstract: A test handler is disclosed in the present invention. The test handler may include a test tray on which a plurality of inserts are arrayed for loading at least one semiconductor device, at least one opening unit for simultaneously opening one part of the plurality of inserts which are arrayed on one part of the test tray, and a test tray transfer apparatus for allowing the opening unit to simultaneously open other parts of the plurality of inserts which are arrayed on another part of the test tray as the test tray is transferred. Therefore, although semiconductor devices to be tested change their sizes, the replaced parts of the test handler are reduced in number, thereby reducing manufacturing cost and replacement work time. The inventive test handler reduces semiconductor devices loading time, reduces jamming, increases teaching efficiency and improves space utilization efficiency. Furthermore, the test handler can be applied to various types of testers.

Abstract: Hole annealing methods are described after erasure of nitride storage memory cells for compensating trapped holes to minimize the holes from detrapping in order to reduce the amount of threshold voltage from drifting significantly higher. A soft hot electron program is used to selected nitride storage memory cells that have been detected to have a threshold voltage that is higher than a presetting threshold voltage (EV) minus a wordline delta X. The effect of the soft electron program neutralizes the excess holes introduced by erasure of nitride storage memory cells that decreases the amount of threshold voltage from drifting higher. In one embodiment, a hole annealing method describes a soft hot electron programming to nitride storage memory cells in a block of nitride memory array that have been determined to have a threshold voltage higher than the presetting threshold voltage minus the wordline delta X.