Abstract: A test handler is disclosed in the present invention. The test handler may include a test tray on which a plurality of inserts are arrayed for loading at least one semiconductor device, at least one opening unit for simultaneously opening one part of the plurality of inserts which are arrayed on one part of the test tray, and a test tray transfer apparatus for allowing the opening unit to simultaneously open other parts of the plurality of inserts which are arrayed on another part of the test tray as the test tray is transferred. Therefore, although semiconductor devices to be tested change their sizes, the replaced parts of the test handler are reduced in number, thereby reducing manufacturing cost and replacement work time. The inventive test handler reduces semiconductor devices loading time, reduces jamming, increases teaching efficiency and improves space utilization efficiency. Furthermore, the test handler can be applied to various types of testers.

Abstract: When a test handler loads semiconductor devices of user trays onto a test tray, the test handler adjusts a front/rear pitch or a right/left pitch between the semiconductor devices, adjusts the right/left pitch or the front/rear pitch, and loads the semiconductor devices. The test handler can sequentially adjust individually the front/rear pitch and the right/left pitch between the semiconductor devices, thereby reducing the apparatus weight and the loading time.

Abstract: A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.

Abstract: A test handler is disclosed. The test handler includes first to third transfers for transferring a user tray, and first to third horizontal movement units suitable for respectively moving the first to third transfers in a horizontal direction. The first to third horizontal movement units are independently operated such that each of the first to third transfers can perform independently horizontal movements. Each of the first to third transfers performs based on its previously allocated function, thereby enhancing test process speed for devices.

Abstract: A pick and place apparatus includes a 1st to an nth device holding element arranged in a lengthwise direction, every one of the 1st to the nth device holding element being connected to its neighboring one(s) of the 1st to the nth device holding element by means of at least one pitch setting ring; a belt having a first coupling part at an upper part thereof for being coupled to the 1st device holding element and a second coupling part at a lower part thereof for being coupled to the nth device holding element; and a driven pulley and a differential pulley. The driven and the differential pulley are rotated by being engaged with the belt to move the 1st and the nth device holding element such that the 1st device holding element moves in a direction opposite to the nth device holding element.

Abstract: A test handler is disclosed. The test handler includes first to third transfers for transferring a user tray, and first to third horizontal movement units suitable for respectively moving the first to third transfers in the horizontal direction. The first to third horizontal movement units are independently operated such that each of the first to third transfers can perform independently horizontal movements. Each of the first to third transfers performs based on its previously allocated function, thereby enhancing test process speed for devices.

Abstract: A test handler includes a loading unit for loading semiconductor devices from customer trays onto a test tray; a test chamber for performing a test for the semiconductor devices loaded on the test tray; a pushing unit having at least one pushing member for pushing the test tray located in the test chamber to be tested, and a press unit for operating the pushing member; a position control unit for adjusting a position of the pushing member to compensate a deviation between the pushing member and the test tray due to a thermal expansion or contraction of any one of the pushing member and the test tray; and an unloading unit for unloading the semiconductor devices loaded on the test tray onto the customer trays after a test for the semiconductor devices is completed.

Abstract: A test handler is disclosed. A posture changing unit for changing a posture of a test tray on which semiconductor devices have been loaded changes the posture of the test tray in a soak chamber. While the posture of the test tray is changed, the devices can be pre-heated/pre-cooled, thereby reducing the soak chamber length and the pre-heating/pre-cooling time.

Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

Abstract: A pick-and-place module for test handlers is disclosed that includes a main body and a kit. The main body forms vacuum paths therein and the kit also forms vacuum passages therein. The kit is detachably mounted to the main body in a hook coupling manner. The pick-and-place module can be applied to all customer trays having different loading capabilities when only the kit of the pick-and-place module needs to be replaced, so there is no need to manufacture the entire pick-and-place module and this reduces manufacturing costs. The pick-and-place module can reduce the amount of resources to be replaced and reduce the replacement time since the kit can be easily removed from the main body of the pick-and-place module in a hook manner.

Abstract: A test handler is disclosed. First and second gripping blocks for respective front and rear test trays to be transferred along a circulation path move together in a circulation direction, but move independently in a direction perpendicular to the circulation path and grip and release independently. The test trays can be transferred by a single power source and interference between an assisting a test and a transferring can be minimized.

Abstract: The present invention relates to a test tray for a test handler. According to this invention, there is disclosed a technique that an insert loaded in a loading part which is arranged in a matrix pattern in a frame of the test tray allows an amount and direction of free movement thereof to be determined in accordance with a location of the loading part, where the insert is loaded, on the matrix, thereby enabling a thermal expansion or contraction of a match plate or the test tray to be compensated.

Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

Abstract: When a test handler loads semiconductor devices of user trays onto a test tray, the test handler adjusts a front/rear pitch or a right/left pitch between the semiconductor devices, adjusts the right/left pitch or the front/rear pitch, and loads the semiconductor devices. The test handler can sequentially adjust individually the front/rear pitch and the right/left pitch between the semiconductor devices, thereby reducing the apparatus weight and the loading time.

Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

Abstract: The present invention relates to a test tray for a test handler. According to this invention, there is disclosed a technique that an insert loaded in a loading part which is arranged in a matrix pattern in a frame of the test tray allows an amount and direction of free movement thereof to be determined in accordance with a location of the loading part, where the insert is loaded, on the matrix, thereby enabling a thermal expansion or contraction of a match plate or the test tray to be compensated.

Abstract: When a test handler loads semiconductor devices of user trays onto a test tray, the test handler adjusts a front/rear pitch or a right/left pitch between the semiconductor devices, adjusts the right/left pitch or the front/rear pitch, and loads the semiconductor devices. The test handler can sequentially adjust individually the front/rear pitch and the right/left pitch between the semiconductor devices, thereby reducing the apparatus weight and the loading time.

Abstract: A test handler is disclosed. A posture changing unit for changing a posture of a test tray on which semiconductor devices have been loaded changes the posture of the test tray in a soak chamber. While the posture of the test tray is changed, the devices can be pre-heated/pre-cooled, thereby reducing the soak chamber length and the pre-heating/pre-cooling time.

Abstract: A test tray for a test handler is disclosed that is loaded with semiconductor devices and then carries them along a predetermined circulation route. The test tray allows one fixing unit to fix a plurality of adjacent insert modules to the receiving spaces of the frame, thereby efficiently using the space of the frame and allowing a relatively large number of insert modules to be installed in the same area, in comparison to the conventional test tray.

Abstract: A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on the mask pattern. Next, a plurality of scattering bar reference sets is applied to the image simulation model so as to generate a plurality of simulation images, respectively. Further, a portion of the simulation images are selected to be a plurality of candidate layouts according to a screening criterion. Next, one of the candidate layouts is determined to be a pattern layout according to a selection rule, and the scattering bar reference set corresponding to the pattern layout is determined to be a scattering bar rule of the mask pattern.