Abstract: A clamping apparatus for clamping a plurality of Hi-Fix boards arranged in a row, includes at least one rotational clamping unit installed to clamp facing end sides of the two or more Hi-Fix boards together, and a plurality of clamping units installed to clamp end sides of the Hi-Fix boards other than the facing sides thereof. The rotational clamping unit includes a clamper installed to rotate about a fixed rotation point to clamp or release the claming of the facing end sides of the two or more Hi-Fix boards, and a driving unit for providing a rotational force to the clamper.

Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a gate dielectric layer, a floating gate, a control gate, an inter-gate dielectric structure and two doped regions. The gate dielectric layer is disposed on a substrate. The floating gate is disposed on the gate dielectric layer. The control gate is disposed on the floating gate. The inter-gate dielectric structure is disposed between the control gate and the floating gate. The inter-gate dielectric structure includes a first oxide layer, a second oxide layer and a charged nitride layer. The first oxide layer is disposed on the floating gate. The second oxide layer is disposed on the first oxide layer. The charged nitride layer is disposed between the first oxide layer and the second oxide layer. The doped regions are disposed in the substrate at two sides of the floating gate, respectively.

Abstract: A test handler is provided, which comprises a test tray, at least one opening unit, and a position changing apparatus. The test tray aligns a plurality of inserts on its side. Each insert loads at least one semiconductor device thereon. The opening unit opens inserts at one part of the one side of the test tray. The position changing apparatus moves at least one opening unit in such a way that the at least one opening units can be located at another part of the one side of the test tray, such that the at least one opening units can open inserts at said another part of the one side of the test tray. The present invention can reduce the number of replaced parts according to change in the semiconductor device size, production cost, and part replacement time.

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a gate dielectric layer, a floating gate, a control gate, an inter-gate dielectric structure and two doped regions. The gate dielectric layer is disposed on a substrate. The floating gate is disposed on the gate dielectric layer. The control gate is disposed on the floating gate. The inter-gate dielectric structure is disposed between the control gate and the floating gate. The inter-gate dielectric structure includes a first oxide layer, a second oxide layer and a charged nitride layer. The first oxide layer is disposed on the floating gate. The second oxide layer is disposed on the first oxide layer. The charged nitride layer is disposed between the first oxide layer and the second oxide layer. The doped regions are disposed in the substrate at two sides of the floating gate, respectively.

Abstract: An opener for a test handler is provided. Even when holding members of inserts of a carrier board are manipulated to release semiconductor devices that have been in a held state, a predetermined distance can remain between an upper surface of the opening plate and a lower surface of the insert, thus preventing the inserts from becoming defective.

Abstract: An insert for a carrier board of a test handler is disclosed. In a first aspect, the latch block applying to the insert is detachably coupled to the insert body. The latch block can be reused, and thus this reduces wastage of resources and eliminates the insert replacement fee. In a second aspect, the insert pocket having hooks is detachably coupled to the insert body. The insert body can be reused. The latch unit is installed to the insert pocket, so that the damaged latch unit can be easily replaced. The insert forms a plurality of holes in the bottom of the loading part thereof, to expose the leads of the semiconductor devices through the holes downwardly. Thus, the insert can load semiconductor devices regardless of the dimensions of the semiconductor devices.

Abstract: A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.

Abstract: A pick-and-place module for test handlers is disclosed that includes a main body and a kit. The main body forms vacuum paths therein and the kit also forms vacuum passages therein. The kit is detachably mounted to the main body in a hook coupling manner. The pick-and-place module can be applied to all customer trays having different loading capabilities when only the kit of the pick-and-place module needs to be replaced, so there is no need to manufacture the entire pick-and-place module and this reduces manufacturing costs. The pick-and-place module can reduce the amount of resources to be replaced and reduce the replacement time since the kit can be easily removed from the main body of the pick-and-place module in a hook manner.

Abstract: A system to support the testing of electronic devices and a temperature control unit for the system are disclosed. A temperature controlling method for a chamber of the system is also disclosed. Low or high temperature air is supplied to the inside of the chamber when the electronic devices are tested at low or high temperature. External air is supplied to the inside of the chamber when the electronic devices are tested at room temperature.

Abstract: A unit for opening an insert of a test tray which comprises an accommodating space for accommodating a semiconductor device and a support for supporting the semiconductor device accommodated in the accommodating space, the unit includes a body, a pair of opening devices provided in the body to open the insert, and a positioning guide unit protruding to be inserted into an accommodating space for a semiconductor device when opening the insert and supporting the semiconductor device that is transferred into the accommodating space to be spaced upward apart from a support provided in the accommodating space.

Abstract: A NAND memory device includes strings of NAND memory cells, where each memory cell includes a charge trapping structure formed over a lightly-doped substrate region. A selected one of the NAND memory cells can be programmed by application of a relatively low program voltage in combination with a previously-applied set-up voltage, which is applied to the substrate for initiating inversion. The inversion in the substrate causes electrons to become hot in the channel regions, including the channel of the selected memory cell. As a result, the relatively lower program voltage can be used at the control gate of the selected memory cell for sufficiently energizing hot electrons to tunnel into the charge trapping structure of the selected memory cell.

Abstract: A test tray for a test handler is disclosed that is loaded with semiconductor devices and then carries them along a predetermined circulation route. The test tray allows one fixing unit to fix a plurality of adjacent insert modules to the receiving spaces of the frame, thereby efficiently using the space of the frame and allowing a relatively large number of insert modules to be installed in the same area, in comparison to the conventional test tray.

Abstract: A test handler and method for operating a test handler for testing semiconductor devices are provided. The test handler includes a test tray located on one side of an opening apparatus in which a plurality of inserts are arrayed, wherein each insert comprises at least one semiconductor device loaded thereon, at least one opening unit for opening inserts at one part of the one side of the test tray, and a position changing apparatus comprises a motor including a driving pulley for moving at least one opening unit along a contact surface of the test tray such that the at least one opening unit changes positions on the test tray and is located at another part of the one side of the test tray in order to open inserts at the other part of the one side of the test tray.

Abstract: A test handler is provided, which comprises a test tray, at least one opening unit, and a position changing apparatus. The test tray aligns a plurality of inserts on its side. Each insert loads at least one semiconductor device thereon. The opening unit opens inserts at one part of the one side of the test tray. The position changing apparatus moves at least one opening unit in such a way that the at least one opening units can be located at another part of the one side of the test tray, such that the at least one opening units can open inserts at said another part of the one side of the test tray. The present invention can reduce the number of replaced parts according to change in the semiconductor device size, production cost, and part replacement time.

Abstract: A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on the mask pattern. Next, a plurality of scattering bar reference sets is applied to the image simulation model so as to generate a plurality of simulation images, respectively. Further, a portion of the simulation images are selected to be a plurality of candidate layouts according to a screening criterion. Next, one of the candidate layouts is determined to be a pattern layout according to a selection rule, and the scattering bar reference set corresponding to the pattern layout is determined to be a scattering bar rule of the mask pattern.

Abstract: A test handler is disclosed. The test handler includes first to third transfers for transferring a user tray, and first to third horizontal movement units suitable for respectively moving the first to third transfers in a horizontal direction. The first to third horizontal movement units are independently operated such that each of the first to third transfers can perform independently horizontal movements. Each of the first to third transfers performs based on its previously allocated function, thereby enhancing test process speed for devices.

Abstract: An opener for a test handler is provided. Even when holding members of inserts of a carrier board are manipulated to release semiconductor devices that have been in a held state, a predetermined distance can remain between an upper surface of the opening plate and a lower surface of the insert, thus preventing the inserts from becoming defective.

Abstract: A pick and place apparatus includes a plurality of device holing elements in a predetermined arrangement; a power supply mechanism for supplying a power for controlling a horizontal pitch between the plurality of device holding elements; a power transmission mechanism for delivering the power from the power supply mechanism to the plurality of device holding elements as a translational force in a horizontal direction; a first linear motion guide mechanism for guiding horizontal movements of some of the plurality of device holding elements; and a second linear motion guide mechanism disposed below the first linear motion guide mechanism, for guiding horizontal movements of the other device holding elements. The plurality of device holding elements are slidably coupled to the first and the second linear motion guide mechanism alternately.