Abstract: Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.

Abstract: Provided is an image processing system and method for analyzing an optic cup and optic disc. The system and method include the following steps. A processor obtains a fundus image. The processor recognizes the optic disc and optic cup in the fundus image using an image recognition model and marks the outlines of the optic disc and optic cup. An interpretation mode is provided so that interpretation data may be generated for risk assessment according to the outlines of the optic disc and optic cup as marked. The image recognition model is a deep learning model trained by a large amount of pre-collected fundus maps. The outlines of the optic cups and optic discs in the fundus images have been marked in advance.

Abstract: A fastener and a toilet seat with the same are provided. The fastener includes a base, two upper holding boards on the base, two stopping levers inserted through the upper holding boards, two elastic expansion parts mounted to the stopping levers, two thread engaging members threaded to the stopping levers, and at least one stopping plate pivotally connected to the stopping lever and rotated between a loose position and a tight position. The toilet seat includes a fastener, a seat pivotally connected to the base, and a lid. When the stopping plate is at the loose position, the thread engaging member, the elastic expansion part, and the stopping lever are allowed to insert through an installation hole of a toilet base. While at the tight position, the stopping lever with the thread engaging member are driven to squeeze the elastic expansion part toward the upper holding board.

Abstract: A method for producing a porous structure electrode with gas permeability and liquid impermeability, includes the following steps: Step 1: mixing a catalytic material having hydrophilicity, a carbon nanotube material, a material with a hydrophilic group, and a carbon black material to form a first slurry, wherein the carbon nanotube material has a specific surface area equal to or greater than the carbon black material; Step 2: mixing the first slurry with an emulsified material to form a second slurry; Step 3: obtaining a film material through a film forming process; Step 4: heating the film material to a first temperature to remove solvent in the film material; Step 5: Repeating steps 3 to 4; and Step 6: heating the film material to a second temperature to remove liquid in the film material, thereby leaving pores in the film material, and allowing the film material to solidify.

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

Abstract: An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.

Abstract: A nitrogen-oxygen separation device includes a housing and a gas separation assembly. The housing comprises a front cover and a rear cover spaced apart to define a space. The gas separation assembly is disposed within the space and includes a front component positioned near the front cover, a rear component positioned near the rear cover, and an electrochemical assembly disposed between the front component and the rear component. The electrochemical assembly includes a cathode current collector, an anode current collector, and an electrolytic reaction membrane positioned between the cathode current collector and the anode current collector.

Abstract: A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A display device includes a first image generating unit and a first waveguide glass. The first image generating unit is configured to emit first light. The first waveguide glass faces toward the first image generating unit. The first waveguide glass includes a first microstructure, two second microstructures and a third microstructure. The first microstructure is located between two ends at the same side of the two second microstructures. The third microstructure is located between the two second microstructures. The third microstructure has a first grating and a second grating. An extending direction of the first grating is different from an extending direction of the second grating. The second microstructure is configured to receive the first light of the first image generating unit transmitted through the first microstructure and transmit the first light to the third microstructure.

Abstract: A thin film transistor includes a bottom gate, a semiconductor layer, a top gate, a first auxiliary conductive pattern, a source, and a drain. The semiconductor layer includes a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first lightly doped region, a second lightly doped region, and a third lightly doped region. The first heavily doped region and the second heavily doped region are respectively located on two sides of the first semiconductor region. Two ends of the second semiconductor region are directly connected to the third heavily doped region and the third lightly doped region, respectively. The top gate is electrically connected to the bottom gate. The source and the drain are respectively electrically connected to the third heavily doped region and the second heavily doped region of the semiconductor layer.

Abstract: In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.

Abstract: An electronic device and a method for determining the intensity of a low-frequency current are provided. The method includes: individually applying a corresponding first current to a body part of a user in N consecutive time intervals, wherein the time intervals include an i-th time interval to an (i+N)-th time interval; obtaining electromyography values of the body part in each time interval; determining a second current corresponding to an (i+N+1)-th time interval based on the first current corresponding to each time interval, the body part, personal information of the user, and the electromyography values of each time interval; and applying a second current to the body part of the user in the (i+N+1)-th time interval.

Abstract: A method of fabricating a semiconductor device is disclosed. A semiconductor substrate is provided. A high-voltage well and a pre-recessed region are formed in the semiconductor substrate. A drift region is formed in the high-voltage well. A recessed channel region is formed adjacent to the drift region. A heavily doped drain region is formed in the drift region and spaced apart from the recessed channel region. An isolation structure is formed between the recessed channel region and the heavily doped drain region in the drift region. The isolation structure overlaps with the pre-recessed region. A buried gate dielectric layer is formed on the recessed channel region. A top surface of the buried gate dielectric layer is lower than a top surface of the heavily doped drain region. A gate is formed on the buried gate dielectric layer.

Abstract: A head-up display includes an image generating unit and a waveguide glass. The waveguide glass faces toward the image generating unit. The waveguide glass includes a first microstructure, a second microstructure and a third microstructure. The first microstructure has a first width. The second microstructure is adjacent to the first microstructure. The third microstructure is adjacent to the second microstructure. The third microstructure has tiling areas adjacent to each other. A gap between the two adjacent tiling areas is less than half of the first width.

Abstract: A method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source/drain and a metal gate. The method may include forming a second silicon nitride layer on the first silicon nitride layer, as a sacrificial layer, and removing the second silicon nitride layer from sidewalls of the first silicon nitride layer formed in the opening. The method may include removing the second silicon nitride layer and the first silicon nitride layer formed at a bottom of the opening, and depositing a metal layer in the opening to form a metal drain in the opening of the semiconductor device.