Abstract: The present invention relates to a method for manufacturing a tubular co-electrolysis cell which is capable of producing synthesis gas from water and carbon dioxide, and a tubular co-electrolysis cell prepared by the preparing method. The present invention comprises a tubular co-electrolysis cell which comprises: a cylindrical support comprising NIO and YSZ: a cathode layer formed on a surface of the cylindrical support, the cathode layer comprising (Sr1-xLax)Ti1-yMy)O3(M=V, Nb, Co, Mn); a solid electrolyte layer formed on the surface of the cathode layer; and an anode layer formed on a surface of the solid electrolyte layer. The tubular co-electrolysis cell manufactured by the method for manufacturing the tubular co-electrolysis cell of the present in has an excellent synthesis gas conversion rate and is capable of producing synthesis gas even at a low over voltage.

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

Abstract: According to an embodiment of the present disclosure, a solid electrolyte for a lithium battery comprises an oxide represented in the following chemical formula and a sintering aid including B2O3 or Bi2O3, wherein the chemical formula is L1+XAXB2?X(PO4)3, wherein A is one or more substances selected from the group consisting of aluminum (Al), chrome (Cr), gallium (Ga), iron (Fe), scandium (Sc), indium (In), ruthenium (Ru), yttrium (Y), and lanthanum (La), B is one or more substances selected from the group consisting of titanium (Ti), germanium (Ge), and zirconium (Zr), and X has a value from 0.1 to 0.5.

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

Abstract: Provided are particle size-controlled, chromium oxide particles or composite particles of iron oxide-chromium alloy and chromium oxide; a preparation method thereof; and use thereof, in which the chromium oxide particles or the composite particles of iron oxide-chromium alloy and chromium oxide having a desired particle size are prepared in a simpler and more efficient manner by using porous carbon material particles having a large pore volume as a sacrificial template. When the chromium oxide particles or the composite particles of iron oxide-chromium alloy and chromium oxide thus obtained are applied to gas-phase and liquid-phase catalytic reactions, they are advantageous in terms of diffusion of reactants due to particle uniformity, high-temperature stability may be obtained, and excellent reaction results may be obtained under severe reaction environment.

Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.

Abstract: According to an embodiment of the present disclosure, a method for preparing a metal bipolar plate for a fuel cell includes drying, crushing, and mixing a Fe—Cr ferrite-based steel powder with a powder of an added element selected from the group consisting of LSM((La0.80Sr0.20)0.95MnO3-x), La2O3, CeO2, and LaCrO3 to prepare a powder mixture, mixing and ball-milling the powder mixture with a solvent and binder into slurry, drying and press-forming the slurry into a pellet, cold isostatic pressing the pellet, and sintering the pellet.

Abstract: The present invention relates to a method of methane steam reforming using a nickel/alumina nanocomposite catalyst. More specifically, the present invention relates to a method of carrying out methane steam reforming using a nickel/alumina nanocomposite catalyst wherein nickel metal nanoparticles are uniformly loaded in a high amount on a support via a melt infiltration method with an excellent methane conversion even under a relatively severe reaction condition of a high gas hourly space velocity or low steam supply, and to a catalyst for this method. In addition, the present invention prepares a nickel/silica-alumina hybrid nanocatalyst by mixing the catalyst prepared by the melt infiltration method as the first catalyst and the nickel silica yolk-shell catalyst as the second catalyst, and applies it to the steam reforming of methane to provide a still more excellent catalytic activity even under the higher temperature of 700° C. or more with the excellent methane conversion.

Abstract: This invention relates to a cathode for a lithium-air battery, a method of manufacturing the same and a lithium-air battery including the same. The method of manufacturing the cathode for a lithium-air battery includes 1) stirring a cobalt salt, triethanolamine and distilled water, thus preparing a cobalt solution, 2) electroplating the cobalt solution on a porous support, thus preparing a cobalt plated porous support, 3) reacting the cobalt plated porous support with a mixture solution including oxalic acid, water and ethanol, thus forming cobalt oxalate on the porous support, and 4) thermally treating the cobalt oxalate.

Abstract: A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.

Abstract: A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage.

Abstract: A wafer includes a first die, a second die, and a scribe lane located between the first die and the second die. The scribe lane includes a first doped silicon region, and does not directly contact the first die and the second die.

Abstract: This invention relates to a cathode for a lithium-air battery, a method of manufacturing the same and a lithium-air battery including the same. The method of manufacturing the cathode for a lithium-air battery includes 1) stirring a cobalt salt, triethanolamine and distilled water, thus preparing a cobalt solution, 2) electroplating the cobalt solution on a porous support, thus preparing a cobalt plated porous support, 3) reacting the cobalt plated porous support with a mixture solution including oxalic acid, water and ethanol, thus forming cobalt oxalate on the porous support, and 4) thermally treating the cobalt oxalate.

Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.

Abstract: A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.

Abstract: A wafer includes a first die, a second die, and a scribe lane located between the first die and the second die. The scribe lane includes a first doped silicon region, and does not directly contact the first die and the second die.

Abstract: A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage.

Abstract: The present invention relates to a Ziegler-Natta catalyst, and more specifically to a Ziegler-Natta catalyst for olefin polymerization which may use a compound of Formula 3 as an internal electron donor to obtain polymers with high activity, wide molecular weight distribution and low content of fine particle.

Abstract: A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

Abstract: An image sensor is provided. A first storage unit stores an image information value corresponding to an image signal provided from a pixel, and a second storage unit stores a reset information value corresponding to a reset signal provided from the pixel. A differential signal comparison unit receives image information value and the reset information value, compares the two values, and outputs a difference value therebetween. A switch unit is switched so that the two input values are transferred in a crossed manner in a first operation period and a second operation period. A digital value providing unit combines a first digital value, which corresponds to an output timing of a first comparison signal in the first operation period, and a second digital value, which corresponds to an output timing of a second comparison signal in the second operation period, and output a digital value corresponding to image information received at the pixel.