Abstract: A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines. Each of the standby currents is generated by each of the bias voltages applied by the bias application unit.

Abstract: The present invention relates to a Ziegler-Natta catalyst, and more specifically to a Ziegler-Natta catalyst for olefin polymerization which may use a compound of Formula 3 as an internal electron donor to obtain polymers with high activity, wide molecular weight distribution and low content of fine particle.

Abstract: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).

Abstract: A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first core voltage to the memory core unit and to control a self refresh operation to be performed at every first self refresh cycle, in a first self refresh mode, and to apply at least one second core voltage to the memory core unit and to control the self refresh operation to be performed at every second self refresh cycle, in a second self refresh mode. In the semiconductor memory, a level of the at least one first core voltage is higher than that of a corresponding one of the at least one second core voltage, and the first self refresh cycle is shorter than the second self refresh cycle.

Abstract: A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

Abstract: An image sensor is provided. A first storage unit stores an image information value corresponding to an image signal provided from a pixel, and a second storage unit stores a reset information value corresponding to a reset signal provided from the pixel. A differential signal comparison unit receives image information value and the reset information value, compares the two values, and outputs a difference value therebetween. A switch unit is switched so that the two input values are transferred in a crossed manner in a first operation period and a second operation period. A digital value providing unit combines a first digital value, which corresponds to an output timing of a first comparison signal in the first operation period, and a second digital value, which corresponds to an output timing of a second comparison signal in the second operation period, and output a digital value corresponding to image information received at the pixel.

Abstract: A semiconductor memory device and method directed to performing a memory operation in a semiconductor memory device are provided. The method includes receiving a write command signal from a memory controller; receiving data from the memory controller, the data including n pieces of data, wherein the k-th piece of data comprises masking data to be masked; and receiving a data masking signal from the memory controller, the data masking signal including enable information that enables data masking, and non-enable information for not enabling data masking, wherein the enable information is used to mask the k-th piece of data. A latency between receiving the write command signal and receiving the enable information is less than a latency between receiving the write command and receiving the k-th piece of data.

Abstract: A bit line sense amplifier circuit for use in a semiconductor memory device, and a control method thereof, in which the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a sense amplifier enable signal to enable the sense amplifier circuit is applied, thereby preventing the bit line sense amplifier circuit of the semiconductor memory device from floating, and preventing or substantially reducing a coupling effect, thereby providing a precise data sensing and amplification operation.

Abstract: A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines. Each of the standby currents is generated by each of the bias voltages applied by the bias application unit.

Abstract: A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first core voltage to the memory core unit and to control a self refresh operation to be performed at every first self refresh cycle, in a first self refresh mode, and to apply at least one second core voltage to the memory core unit and to control the self refresh operation to be performed at every second self refresh cycle, in a second self refresh mode. In the semiconductor memory, a level of the at least one first core voltage is higher than that of a corresponding one of the at least one second core voltage, and the first self refresh cycle is shorter than the second self refresh cycle.

Abstract: A semiconductor memory device and related test method are disclosed. Test data is defined from a group of M test bits selected from either input data or corresponding output data. A parallel bit test is then conducted on the test data. The M test bits include N test bits, where N is less than M, selected on a bit by bit basis from the output data, and L test bits, where N+L=M, selected from the input data. The selection of input data may be made in accordance with a don't care case for selected test data.

Abstract: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

Abstract: A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory.

Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR to (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).

Abstract: A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during n (n is positive integer) periods of a clock signal.

Abstract: A semiconductor memory device and method directed to performing a memory operation in a semiconductor memory device, which include receiving data and a data masking signal corresponding to a portion of the received data configured to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory, and further configuring different timing parameters of the received data and the data masking signal for executing the write command without writing the at least a portion of the received data into the memory.

Abstract: A row active time control circuit is described that includes a master signal generating circuit and a row active control signal generating circuit. The master signal generating circuit generates one or more row active master signals based on an active command signal, a pre-charge command signal, and one or more row active control signals. The row active control signal generating circuit generates a pulse signal that oscillates based on the one or more row active master signals. The row active control signal also generates the one or more row active control signals by dividing a frequency of the generated pulse signal.

Abstract: There are provided a semiconductor memory device and a burn-in test method thereof. A semiconductor memory device according to an aspect of the invention includes a plurality of memory cell blocks, each of which includes a plurality of memory cells that are respectively coupled to a plurality of word lines and a plurality of bit lines, a word line control unit activating word lines in memory cell blocks that correspond to row address signals and word lines in memory cell blocks that do not correspond to the row address signals, during a test operation, and a write circuit writing data in the memory cell blocks that correspond to the row address signals and not writing data in the memory cell blocks that do not correspond to the row address signals, during the test operation.

Abstract: Provided is a semiconductor memory device and method that can control internal supply voltages independently. The semiconductor memory device includes a memory cell array, a reference voltage generating unit, an internal reference voltage generating unit, and an internal supply voltage generating unit. The reference voltage generating unit outputs a reference voltage in response to an external voltage. The internal reference voltage generating unit converts the reference voltage into a plurality of internal reference voltages, and outputs the plurality of internal reference voltages. The internal supply voltage generating unit converts the plurality of internal reference voltages into a plurality of internal supply voltages, and outputs the plurality of internal supply voltages. A first internal reference voltage is used to generate a first internal supply voltage and a second internal reference voltage is used to generate a second internal supply voltage.