Patents by Inventor Hyoung Lim
Hyoung Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7612573Abstract: A probe sensing pad used to detect a position of a probe needle includes a probe area, at least two sensing regions contacting peripheral portions of the probe area, sensing elements of different electrical characteristics connected to corresponding sensing regions, and at least one isolation region for electrically insulting the sensing regions. The position of the probe needle relative to the probe sensing pad may be rapidly detected and automatically corrected toward a desired contact site of the probe sensing pad depending upon the voltage measured by a probe needle contacting the probe sensing pad. That is, the measured voltage will have a first value if deflected in a first direction, a second value (different from the first) if deflected in a second direction, and so on. The position of the probe needle can be corrected based on this measurement.Type: GrantFiled: November 30, 2006Date of Patent: November 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kun-Up Kim, Chang-Sik Kim, Doo-Seon Lee, Jong-Hyoung Lim
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Patent number: 7609547Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).Type: GrantFiled: December 21, 2007Date of Patent: October 27, 2009Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Dong Yun Jeong, Jae Hyoung Lim, Young Jin Park, Kye Nam Lee, In Woo Jang, Seaung Suk Lee, Chang Shuk Kim
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Patent number: 7554866Abstract: An input/output sense amplifier (IOSA) controller of a semiconductor memory device includes an auto pulse generator and a latch enable signal generating circuit. The auto pulse generator generates an auto pulse signal having a first pulse shape. The latch enable signal generating circuit generates a first latch enable signal having a second pulse shape in response to an auto pulse signal in normal mode, and generates a second latch enable signal having a level shape that is enabled for long duration in response to the write enable bar signal in test mode. Accordingly, the semiconductor memory device including the IOSA controller may safely test a characteristic of the IOSA.Type: GrantFiled: June 21, 2007Date of Patent: June 30, 2009Assignee: Samsung Electroncis Co., Ltd.Inventors: Jang-won Moon, Jong-Hyoung Lim
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Publication number: 20090097349Abstract: A row active time control circuit is described that includes a master signal generating circuit and a row active control signal generating circuit. The master signal generating circuit generates one or more row active master signals based on an active command signal, a pre-charge command signal, and one or more row active control signals. The row active control signal generating circuit generates a pulse signal that oscillates based on the one or more row active master signals. The row active control signal also generates the one or more row active control signals by dividing a frequency of the generated pulse signal.Type: ApplicationFiled: January 10, 2008Publication date: April 16, 2009Inventors: Ji-Hyun Lee, Jong-Hyoung Lim
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Publication number: 20090044063Abstract: A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.Type: ApplicationFiled: October 12, 2007Publication date: February 12, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Yong-Hwan Cho, Byung-Heon Kwak, Hyun-Soon Jang, Jae-Hoon Joo, Seung-Whan Seo, Jong-Hyoung Lim
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Publication number: 20090016131Abstract: A bit line sense amplifier circuit for use in a semiconductor memory device, and a control method thereof, in which the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a sense amplifier enable signal to enable the sense amplifier circuit is applied, thereby preventing the bit line sense amplifier circuit of the semiconductor memory device from floating, and preventing or substantially reducing a coupling effect, thereby providing a precise data sensing and amplification operation.Type: ApplicationFiled: July 2, 2008Publication date: January 15, 2009Inventors: Ji-Hun Lee, Jong-Hyoung Lim
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Patent number: 7466616Abstract: A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.Type: GrantFiled: August 4, 2006Date of Patent: December 16, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Man Byun, Sang-Seok Kang, Jong-Hyoung Lim
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Publication number: 20080296644Abstract: A CMOS image sensor includes an image transfer transistor therein. This image transfer transistor includes a semiconductor channel region of first conductivity type and an electrically conductive gate on the semiconductor channel region. A gate insulating region is also provided. The gate insulating region extends between the semiconductor channel region and the electrically conductive gate. The gate insulating region includes a nitridated insulating layer extending to an interface with the electrically conductive gate and a substantially nitrogen-free insulating layer extending to an interface with the semiconductor channel region. The nitridated insulating layer may be a silicon oxynitride (SiON) layer.Type: ApplicationFiled: August 6, 2008Publication date: December 4, 2008Inventors: Young-Sub You, Jung-Hwan Oh, Yong-Woo Hyung, Hun-Hyoung Lim
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Patent number: 7397715Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal and transmitting address signals in response to the operation mode selection signal; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal. All redundancy cells can be selected and tested based on the external command signal and the address signal, and thus it is possible to check all redundancy cells for defects in advance even after the semiconductor memory device is packaged, and to enable only non-defective redundancy cells to be substituted for defective regular cells.Type: GrantFiled: June 9, 2006Date of Patent: July 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyoung Lim, Sang-Man Byun
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Publication number: 20080159044Abstract: Provided is a semiconductor memory device and method that can control internal supply voltages independently. The semiconductor memory device includes a memory cell array, a reference voltage generating unit, an internal reference voltage generating unit, and an internal supply voltage generating unit. The reference voltage generating unit outputs a reference voltage in response to an external voltage. The internal reference voltage generating unit converts the reference voltage into a plurality of internal reference voltages, and outputs the plurality of internal reference voltages. The internal supply voltage generating unit converts the plurality of internal reference voltages into a plurality of internal supply voltages, and outputs the plurality of internal supply voltages. A first internal reference voltage is used to generate a first internal supply voltage and a second internal reference voltage is used to generate a second internal supply voltage.Type: ApplicationFiled: August 1, 2007Publication date: July 3, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Jang-won Moon, Young-hyun Jun, Jong-hyoung Lim
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Publication number: 20080151655Abstract: There are provided a semiconductor memory device and a burn-in test method thereof. A semiconductor memory device according to an aspect of the invention includes a plurality of memory cell blocks, each of which includes a plurality of memory cells that are respectively coupled to a plurality of word lines and a plurality of bit lines, a word line control unit activating word lines in memory cell blocks that correspond to row address signals and word lines in memory cell blocks that do not correspond to the row address signals, during a test operation, and a write circuit writing data in the memory cell blocks that correspond to the row address signals and not writing data in the memory cell blocks that do not correspond to the row address signals, during the test operation.Type: ApplicationFiled: December 19, 2007Publication date: June 26, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Dae-sun Kim, Jong-hyoung Lim, Sang-ki Son
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Patent number: 7391254Abstract: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first node. The first output voltage is maintained between the first and second reference voltages. The second driving circuit receives a feedback voltage from a second node voltage and generates a second output voltage based on third and fourth reference voltages to provide the second output voltage to the second node. The second output voltage is maintained between the third and fourth reference voltages, and the second output voltage of the second node is provided as an internal supply voltage. The resistive device is coupled between the first and second nodes.Type: GrantFiled: September 14, 2006Date of Patent: June 24, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyoung Lim, Sang-Seok Kang, Sang-Man Byun
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Patent number: 7382641Abstract: A non-volatile ferroelectric memory device senses a cell data at high speed. Preferably, the non-volatile ferroelectric memory device includes a plurality of cell array blocks, a plurality of sense amplifier units, a plurality of sense amplifier units, a plurality of local data buses, a global data bus, and a plurality of data bus switch arrays. Each of the plurality of cell array blocks has a hierarchical bit line architecture including sub bit lines and a main bit line group corresponding to a plurality of unit cells for storing differential data. The plurality of sense amplifier units, corresponding one-by-one to the cell array blocks, sense and amplify the differential data induced on the main bit line group during a sensing operation. The plurality of local data buses, corresponding one-by-one to the sense amplifier units, transfer the differential data outputted from the sense amplifier units and differential data to be transferred to the sense amplifier units.Type: GrantFiled: June 30, 2004Date of Patent: June 3, 2008Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Dong Yun Jeong, Jae Hyoung Lim
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Publication number: 20080052567Abstract: A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory.Type: ApplicationFiled: March 30, 2007Publication date: February 28, 2008Inventors: Jong-Hyoung Lim, Sang-Seok Kang
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Patent number: 7333361Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).Type: GrantFiled: February 21, 2006Date of Patent: February 19, 2008Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Dong Yun Jeong, Jae Hyoung Lim, Young Jin Park, Kye Nam Lee, In Woo Jang, Seaung Suk Lee, Chang Shuk Kim
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Publication number: 20080022170Abstract: A semiconductor memory device and related test method are disclosed. Test data is defined from a group of M test bits selected from either input data or corresponding output data. A parallel bit test is then conducted on the test data. The M test bits include N test bits, where N is less than M, selected on a bit by bit basis from the output data, and L test bits, where N+L=M, selected from the input data. The selection of input data may be made in accordance with a don't care case for selected test data.Type: ApplicationFiled: July 6, 2007Publication date: January 24, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-man BYUN, Sang-cheol KIM, Jong-hyoung LIM, Gwan-pyo HONG
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Publication number: 20080008011Abstract: An input/output sense amplifier (IOSA) controller of a semiconductor memory device includes an auto pulse generator and a latch enable signal generating circuit. The auto pulse generator generates an auto pulse signal having a first pulse shape. The latch enable signal generating circuit generates a first latch enable signal having a second pulse shape in response to an auto pulse signal in normal mode, and generates a second latch enable signal having a level shape that is enabled for long duration in response to the write enable bar signal in test mode. Accordingly, the semiconductor memory device including the IOSA controller may safely test a characteristic of the IOSA.Type: ApplicationFiled: June 21, 2007Publication date: January 10, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Jang-won Moon, Jong-Hyoung Lim
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Publication number: 20070180853Abstract: There is provided a refrigerator. The refrigerator includes a compressor for compressing a refrigerant, a condenser for heat-exchanging the compressed refrigerant with ambient air, an expansion member for expanding the heat-exchanged refrigerant, a condensing pipe interconnecting the condenser and the expansion member, a vaporizer for heat-exchanging the expanded refrigerant with a cooling air in a freezing or cooling chamber, and a suction pipe interconnecting the vaporizer and the compressor and associated with the condensing pipe to allow a heat exchange between the suction pipe and the condensing pipe.Type: ApplicationFiled: January 2, 2007Publication date: August 9, 2007Applicant: LG ELECTRONICS INC.Inventors: Hyoung LIM, Sung JHEE, Nam CHO
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Patent number: 7212428Abstract: A non-volatile ferroelectric memory device having differential datacomprises a plurality of cell array blocks and a data buffer unit. Each of the plurality of cell array blocks includes cell arrays and sense amplifiers. The cell array has a hierarchical bit line architecture and are divided into top and bottom groups where differential data are stored in a plurality of unit cells corresponding to differential main bit lines of the divided cell arrays. The sense amplifiers are positioned between the divided cell array groups for sensing the differential data. The data buffer unit temporarily stores a read data sensed by the sense amplifier and a write data received through a data I/O port.Type: GrantFiled: June 28, 2004Date of Patent: May 1, 2007Assignee: Hynix Semiconductor Inc.Inventors: Dong Yun Jeong, Jae Hyoung Lim, Hee Bok Kang
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Patent number: 7212450Abstract: Disclosed is a non-volatile ferroelectric memory device having differential data, the device including: a plurality of cell array block groups having a hierarchy bit line structure and storing differential data; a common data bus being shared by a plurality of the cell array block groups, and transferring sensing voltages induced by the differential data; a column selection control unit selectively applying to the common data bus the induced sensing voltages of two main bit lines of the cell array block group according to the differential data; and a sense amp unit receiving the sensing voltages through the common data bus, comparing two sensing voltages induced by the differential data, and sensing the cell data. Therefore, the non-volatile ferroelectric memory device of the invention is capable of sensing a cell data more stably, independent of external factors and the state of a cell, by simultaneously sensing the stored data (differential data) in two unit cells and detecting the cell data.Type: GrantFiled: June 30, 2004Date of Patent: May 1, 2007Assignee: Hynix Semiconductor Inc.Inventors: Jae Hyoung Lim, Dong Yun Jeong, Hee Bok Kang