Abstract: A probe sensing pad used to detect a position of a probe needle includes a probe area, at least two sensing regions contacting peripheral portions of the probe area, sensing elements of different electrical characteristics connected to corresponding sensing regions, and at least one isolation region for electrically insulting the sensing regions. The position of the probe needle relative to the probe sensing pad may be rapidly detected and automatically corrected toward a desired contact site of the probe sensing pad depending upon the voltage measured by a probe needle contacting the probe sensing pad. That is, the measured voltage will have a first value if deflected in a first direction, a second value (different from the first) if deflected in a second direction, and so on. The position of the probe needle can be corrected based on this measurement.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal and transmitting address signals in response to the operation mode selection signal; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal. All redundancy cells can be selected and tested based on the external command signal and the address signal, and thus it is possible to check all redundancy cells for defects in advance even after the semiconductor memory device is packaged, and to enable only non-defective redundancy cells to be substituted for defective regular cells.

Abstract: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first node. The first output voltage is maintained between the first and second reference voltages. The second driving circuit receives a feedback voltage from a second node voltage and generates a second output voltage based on third and fourth reference voltages to provide the second output voltage to the second node. The second output voltage is maintained between the third and fourth reference voltages, and the second output voltage of the second node is provided as an internal supply voltage. The resistive device is coupled between the first and second nodes.

Abstract: Provided is a semiconductor device including a plurality of fuse circuits. Each of the fuse circuits includes: a first signal generator generating a first signal to a first node in response to a power-up signal; a pull-down transistor pulling down a second node in response to the first signal; a pull-up transistor and a fuse which are connected in series between a power supply voltage and the second node and pulling up the second node in response to the first signal when the fuse is not cut; a buffer buffering a signal output from the second node and generating a control signal; and a standby reset transistor resetting the second node in response to the control signal output from the buffer, wherein the pull-down transistor and the standby reset transistor have threshold voltages lower than a threshold voltage of the buffer. Also, each of the fuse circuits further includes an active reset transistor resetting the second node in the active mode in response to the reset control signal.

Abstract: A circuit and method for test mode entry of a semiconductor memory device are provided. In a method of entering a semiconductor memory device into a test mode, an internal clock is generated in response to an external clock when a first condition is satisfied. An address combination signal is generated based on a first address combination and the internal clock. The semiconductor memory device is entered into the test mode using the internal clock and the address combination signal.

Abstract: A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.

Abstract: A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during n (n is positive integer) periods of a clock signal.

Abstract: Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device comprises a memory cell array consisting of a plurality of repetitive cell units; a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array; switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively; and a write driver for supplying a write data voltage to the data line and the complementary data line, wherein the column selection line signal is generated during a write recovery time.

Abstract: A reference voltage generator generates an output reference voltage having various voltage levels. The reference voltage generator includes an amplifier to amplify a difference between a feedback reference voltage and a feedback voltage to generate an amplified signal, a current driving circuit to provide a current signal in response to the amplified signal, a scaler circuit to generate feedback voltage signals and reference voltage signals in response to the current signal, and a feedback voltage selecting circuit to select one of the feedback voltage signals in response to a control signal, and to provide the selected feedback voltage signal to the operational amplifier as the feedback voltage.

Abstract: A circuit and method for test mode entry of a semiconductor memory device are provided. In a method of entering a semiconductor memory device into a test mode, an internal clock is generated in response to an external clock when a first condition is satisfied. An address combination signal is generated based on a first address combination and the internal clock. The semiconductor memory device is entered into the test mode using the internal clock and the address combination signal.

Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).

Abstract: A DLL power supply of the integrated circuit memory device supplies power to the DLL circuit, and a control signal generator controls the DLL power supply to selectively supply power to the DLL circuit during a refresh mode of the integrated circuit memory device based on a selection signal.

Abstract: Apparatus and method for controlling an operation of a blower fan are provided. In the apparatus and method, a temperature of an evaporator is measured, and an amount of cool air remaining in the evaporator is computed from the measured temperature of the evaporator such that the cool air of the evaporator can be sufficiently used. According to the present invention, a use efficiency of the refrigerator can be further enhanced.

Abstract: Provided is a radiating apparatus of a built-in refrigerator that can improve heat radiation in a machine room of the refrigerator installed in a built-in cabinet. The radiating apparatus includes: a refrigerator body installed in a built-in cabinet; a machine room disposed at a rear lower side of the refrigerator body; a compressor installed at one side of the machine room; a condenser and a blower fan installed at the other side of the machine room; and an airflow guide member installed between the blower fan and the condenser, for guiding a suction of an external air toward the other side of the machine room and guiding a discharge of an air that has exchanged heat in the other side of the machine room.

Abstract: A radiating apparatus of a built-in refrigerator includes an airflow guide that separates a condenser from a blower fan in order to prevent a cool air and a hot air from mixing together, thereby increasing an efficiency of the built-in refrigerator.

Abstract: Disclosed is an icemaker for a refrigerator includes an ice mold for receiving water and freezing the water to ice, an ejector pivotally installed on the ice mold to eject the ice out of the ice mold, a motor for operating the ejector, a heater body disposed enclosing the ice mold to separate the ice from an inner surface of the ice mold by uniformly heating the ice mold, and a heating coil for applying induced electromotive power to the heater body, thereby allowing the heater body to generate heat.

Abstract: A sealing structure of a refrigerator is provided. The structure includes: a gasket formed at a door of the refrigerator; at least one air pocket formed at the gasket; and at least one convection cut-off member disposed in the air pocket, for suppressing natural convection.

Abstract: Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device comprises a memory cell array consisting of a plurality of repetitive cell units; a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array; switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively; and a write driver for supplying a write data voltage to the data line and the complementary data line, wherein the column selection line signal is generated during a write recovery time.

Abstract: In a data output circuit for reducing a skewing error of a data signal, a first inversion unit receives a first data signal of an operating voltage level and inverts the received first data signal to obtain a first inverted data signal. If a first power supply voltage of an output voltage level is different from a second power supply voltage with the operating voltage level by at least a predetermined voltage level, a first voltage compensation unit compensates for the voltage level of the first inverted data signal to obtain a first driving signal. A second inversion unit receives a second data signal with the operating voltage level and inverts the received second data signal to obtain a second inverted data signal. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, a second voltage compensation unit compensates for the voltage level of the second inverted data signal to obtain a second driving signal.

Abstract: A DLL power supply of the integrated circuit memory device supplies power to the DLL circuit, and a control signal generator controls the DLL power supply to selectively supply power to the DLL circuit during a refresh mode of the integrated circuit memory device based on a selection signal.