Abstract: A threshold switching device may include: a first electrode layer; a second electrode layer; a first insulating layer interposed between the first and second electrode layers, and provided adjacent to the first electrode layer; and a second insulating layer interposed between the first and second electrode layers, and provided adjacent to the second electrode layer, wherein the first and second insulating layers contain a plurality of neutral defects, a concentration of the plurality of neutral defects being at a maximum along a first interface between the first insulating layer and the second insulating layer, and wherein the threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.

Abstract: An electronic device includes a semiconductor memory unit, which includes resistive memory cells; an access circuit to apply, during a write operation, a write voltage across a selected one of the resistive memory cells in a first or second direction; first switching units, each of which is disposed between the access circuit and a first end of a corresponding one of the resistive memory cells and turned on in response to a first voltage having a level higher than a predetermined level when the corresponding resistive memory cell is selected during the write operation; and second switching units, each of which is disposed between the access circuit and a second end of the corresponding resistive memory cell and turned on in response to a second voltage having a level equal to or lower than the predetermined level when the corresponding resistive memory cell is selected during the write operation.

Abstract: A neuromorphic device includes an input device; an output device; and a neural network including a first synapse network and a second synapse network between the input device and the output device. The first synapse network includes a first synapse system having higher learning efficiency than the second synapse network, and the second synapse network includes a second synapse system having more excellent data retention capability than the first synapse network.

Abstract: A neuromorphic device may include: pre-synaptic neurons; row lines extending in a first direction from the pre-synaptic neurons, respectively; post-synaptic neurons; column lines extending in a second direction from the post-synaptic neurons, respectively, the second direction crossing the first direction; and synapses arranged in intersection regions between the row lines and the column lines. The synapses may include resistor interconnections having various fixed resistance values. The synapses may be programmed with at least one pattern based on the various fixed resistance values.

Abstract: A neuromorphic device having synapses may include: a top electrode; a bottom electrode; and a variable resistive layer disposed between the top electrode and the bottom electrode. The variable resistive layer may include a plurality of carrier traps distributed at multiple energy levels.

Abstract: An electronic device including a semiconductor memory unit that includes: a first access line coupled to a first memory cell; a second access line coupled to a second memory cell for replacing the first memory cell when the first memory cell is a failure memory cell; a first driving block coupled to one of the first access line and the second access line, and suitable for driving said one of the first access line and the second access line with a first voltage when the first memory cell is accessed; and a first repair coupling block suitable for selectively coupling the first access line and the second access line based on whether the first memory cell is a failure memory cell or not when the first memory cell is accessed.

Abstract: A switching device includes a first electrode and a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. The electrolyte layer includes a first layer charged with negative charges and a second layer charged with positive charges.

Abstract: A method for updating a weight of a synapse of a neuromorphic device is provided. The synapse may include a transistor and a memristor. The memristor may have a first electrode coupled to a source electrode of the transistor. The method may include inputting a row spike to a drain electrode of the transistor at a first time; inputting a column spike to a second electrode of the memristor at a second time; inputting a row pulse to the drain electrode of the transistor at a third time that is delayed by a first delay time from the second time; inputting a column pulse to the second electrode of the memristor at a fourth time that is delayed by a second delay time from the second time; and inputting a gating pulse to a gate electrode of the transistor at a fifth time that is delayed by a third delay time from the fourth time.

Abstract: A neuromorphic device includes a synapse. The synapse includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, a reactive metal layer disposed between the oxygen-containing layer and the second electrode, and an oxygen diffusion-retarding layer disposed between the reactive metal layer and the oxygen-containing layer. The oxygen-containing layer includes a P-type material and oxygen ions. The reactive metal layer reacts with the oxygen ions of the oxygen-containing layer. The oxygen diffusion-retarding layer includes an N-type material and interferes with a movement of the oxygen ions from the oxygen-containing layer to the reactive metal layer. An interface between the oxygen-containing layer and the oxygen diffusion-retarding layer is a P-N junction.

Abstract: A neuromorphic device may include: a plurality of row lines extending in a first direction; a plurality of additional row lines extending in the first direction; a plurality of column lines extending in a second direction that crosses the first direction; and a plurality of synapses positioned at intersections of the row lines, the additional row lines, and the column lines, wherein each of the synapses includes a transistor comprising a floating gate, a control gate insulated from the floating gate, a first junction, and a second junction, the control gate being coupled to a corresponding one of the plurality of row lines, the first junction being coupled to a corresponding one of the plurality of additional row lines, the second junction being coupled to a corresponding one of the plurality of column lines.

Abstract: A neuromorphic device having synapses may include: a top electrode; a bottom electrode; and a variable resistive layer disposed between the top electrode and the bottom electrode. The variable resistive layer may include a plurality of carrier traps distributed at multiple energy levels.

Abstract: A neuromorphic device includes a row line extending in a first direction; a column line disposed over the row line, the column line extending in a second direction perpendicular to the first direction; a plurality of gating lines disposed between the row line and the column line; and a synapse disposed between the row line and the column line, the synapse passing through the plurality of gating lines.

Abstract: A neuromorphic device may include: a pre-synaptic neuron; a row line electrically coupled to the pre-synaptic neuron; a post-synaptic neuron; a column line electrically coupled to the post-synaptic neuron; and a synapse disposed at a cross point between the row line and the column line. The post-synaptic neuron may include: a first integrator electrically coupled to the synapse; a second integrator electrically coupled to the first integrator; and a comparator electrically coupled to the second integrator.

Abstract: A neuromorphic device includes a substrate; a first electrode and a second electrode that are disposed over the substrate, extend in a first direction, and are spaced apart in a second direction; a stack structure between the first electrode and the second electrode, which includes reactive metal layers alternately stacked with one or more insulating layers; an oxygen-containing layer between the first electrode and the stack structure, which includes oxygen ions; and an oxygen diffusion-retarding layer between the stack structure and the oxygen-containing layer. The first direction is perpendicular to a top surface of the substrate, and the second direction is parallel to the top surface of the substrate. Each reactive metal layer may react with the oxygen ions to form a dielectric oxide layer. The oxygen diffusion-retarding layer interferes with a movement of the oxygen ions. A thickness of the oxygen diffusion-retarding layer varies along the first direction.

Abstract: A neuromorphic device includes a synapse. The synapse includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, the oxygen-containing layer including oxygen ions, and a stack structure disposed between the oxygen-containing layer and the second electrode, the stack structure including a plurality of reactive metal layers alternately arranged with a plurality of oxygen diffusion-retarding layers. The plurality of reactive metal layers are capable of reacting with oxygen ions of the oxygen-containing layer. The plurality of oxygen diffusion-retarding layers interfere with a movement of the oxygen ions from the oxygen-containing layer to the plurality of reactive metal layers.

Abstract: A neuromorphic device may include: a plurality of pre-synaptic neurons; row lines extending in a row direction from the plurality of pre-synaptic neurons; a plurality of post-synaptic neurons; column lines extended in a column direction from the plurality of post-synaptic neurons; a plurality of synapses arranged at intersections between the row lines and the column lines; a plurality of first control blocks; and first control lines extending from the control blocks. The first control lines may be electrically connected to the plurality of synapses.

Abstract: A learning method for synapses of a neuromorphic device may include generating and inputting, by a pre-synaptic neuron, a first pre-synaptic pulse to a plurality of synapses at a first start time, the plurality of synapses being coupled to the pre-synaptic neuron; generating and inputting, by a first post-synaptic neuron, a first post-synaptic pulse to a first synapse of the plurality of synapses at a first delayed time that is delayed by a first delay amount from the first start time, the first synapse being coupled to the first post-synaptic neuron; and generating and inputting, by a second post-synaptic neuron, a second post-synaptic pulse to a second synapse of the plurality of synapses at a second delayed time that is delayed by a second delay amount from the first start time, the second synapse being coupled to the second post-synaptic neuron.

Abstract: A neuromorphic device may include: a pre-synaptic neuron; a plurality of post-synaptic neurons; and a plurality of synapses electrically connected to the pre-synaptic neuron and electrically connected to the plurality of post-synaptic neurons. Each of the post-synaptic neurons may include: an integrator; a main comparator having a first input port connected to an output port of the integrator; and a first sub comparator having a first input port connected to the output port of the integrator.

Abstract: A method reads data from a synapse which includes a transistor and a variable resistor. The transistor has a gate electrode, a first electrode and a second electrode. The variable resistor has a first electrode connected to the second electrode of the transistor. The method includes applying a read voltage to the gate electrode of the transistor, applying a pre-synaptic voltage to the first electrode of the transistor, and applying a post-synaptic voltage to a second electrode of the variable resistor. The read voltage is lower than the threshold voltage of the transistor.

Abstract: A neuromorphic device includes a synapse. The synapse, according to an embodiment, includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, the oxygen-containing layer including oxygen ions, and a reactive metal layer disposed between the oxygen-containing layer and the second electrode. The oxygen-containing layer includes oxygen ions. The reactive metal layer is capable of reacting with the oxygen ions of the oxygen-containing layer. A width of the reactive metal layer decreases along a direction toward the oxygen-containing layer from the second electrode.