Patents by Inventor In Chang Hwang

In Chang Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200180474
    Abstract: A fold and dive seat for a vehicle is provided with a seat-cushion tilting mechanism, a fold and dive mechanism, and a seatback reclining mechanism so as to simultaneously performed both a seatback reclining operation and a tilting operation of a front portion of a seat cushion. The fold and dive seat reduces by evenly dispersing a body pressure over a passenger's upper body and lower body.
    Type: Application
    Filed: April 15, 2019
    Publication date: June 11, 2020
    Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION, DAECHANG SEAT CO.,LTD-DONGTAN, HYUNDAI TRANSYS INC.
    Inventors: Hyun Kyu MOON, Seon Chae NA, Jung Sang YOU, Chan Ho JUNG, Sang Beom HWANG, In Chang HWANG, Myung Soo LEE, Jeong Soo KIM, Eom Seok YOO
  • Patent number: 10611417
    Abstract: A rear spoiler apparatus for a vehicle may include a main flap which is deployed by an operation force from an actuator and a support flap which is additionally deployed from the main flap, in which the support flap rotates to open together when the main flap rotates and the open angle of the support flap is greater than the open angle of the support flap.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: April 7, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corp.
    Inventors: Hak Lim Kim, Min Sik Chung, Sang Hyun Park, Ui Chang Hwang, Seung Hwan Kim, Dong Guk Lee, Koo Cheol Kang
  • Publication number: 20190378446
    Abstract: A health monitoring device included in a large area display (LAD) with at least one display computers comprises a universal asynchronous receiver-transmitter (UART) configured to produce a test path by communicating with a processor of the display computer, a field programmable gate array (FPGA) configured to transmit a test signal to a terminal of the display computer and receive a test result, an ethernet unit configured to communicate with a test terminal connected with the LAD to transmit a monitoring signal to the test terminal, and a micro-controller configured to gather an operation state of the display computer and produce a measurement signal according to the test result.
    Type: Application
    Filed: July 27, 2018
    Publication date: December 12, 2019
    Inventor: Byeung Chang HWANG
  • Publication number: 20190294851
    Abstract: A display panel for providing sensing light to an optical fingerprint sensor and a fingerprint sensing system including the display panel are provided. A display panel according to an example embodiment includes a window glass, a phase change layerunder the window glass and delaying a phase of light, a polarizing plate under the phase change layer, a pixel layer under the polarizing plate and having a plurality of pixels each emitting light, and a substrate under the pixel layer and configured to transmit the sensing light generated by scattering light emitted from at least a part of the plurality of pixels by a fingerprint on the window glass.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 26, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-young CHUNG, Sang-hyun Cho, Hee-chang Hwang, Sung-mok Lee, Jong-sung Lee
  • Patent number: 10410979
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 10, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Wen Chu
  • Publication number: 20190248430
    Abstract: A rear spoiler apparatus for a vehicle may include a main flap which is deployed by an operation force from an actuator and a support flap which is additionally deployed from the main flap, in which the support flap rotates to open together when the main flap rotates and the open angle of the support flap is greater than the open angle of the support flap.
    Type: Application
    Filed: July 16, 2018
    Publication date: August 15, 2019
    Applicants: Hyundai Motor Company, Kia Motors Corp.
    Inventors: Hak Lim KIM, Min Sik CHUNG, Sang Hyun PARK, Ui Chang HWANG, Seung Hwan KIM, Dong Guk LEE, Koo Cheol KANG
  • Patent number: 10374129
    Abstract: An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor substrate; at least one via hole penetrating the compound semiconductor substrate, a top of an inner surface of the via hole is defined by the front-side metal layer; at least one seed metal layer, at least one backside metal layer and at least one diffusion barrier layer sequentially formed on a bottom surface of the compound semiconductor substrate and the inner surface of the via hole, the seed metal layer and the front-side metal layer are electrically connected through the via hole; a die attachment metal layer formed on a bottom surface of the diffusion barrier layer other than the via hole and an adjacent area near the via hole. The diffusion barrier layer prevents the backside metal layer from diffusing into the die attachment metal layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 6, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Shu Chen Chen, Huang-Wen Wang, Walter Tony Wohlmuth
  • Publication number: 20190210973
    Abstract: Provided are compounds having Formula (1), compositions thereof, and methods of modulating CFTR activity. Also provided are methods of treating a condition associated with decreased CFTR activity comprising administering to a subject an effective amount of a compound of Formula (1), optionally with other therapeutic agent(s).
    Type: Application
    Filed: January 4, 2019
    Publication date: July 11, 2019
    Inventors: Lianhai LI, Tzyh-Chang HWANG, Xiaoqin Zou
  • Publication number: 20190131244
    Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.
    Type: Application
    Filed: November 27, 2017
    Publication date: May 2, 2019
    Inventors: Chang-Hwang HUA, Yi-Wei LIEN
  • Publication number: 20190096755
    Abstract: An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor substrate; at least one via hole penetrating the compound semiconductor substrate, a top of an inner surface of the via hole is defined by the front-side metal layer; at least one seed metal layer, at least one backside metal layer and at least one diffusion barrier layer sequentially formed on a bottom surface of the compound semiconductor substrate and the inner surface of the via hole, the seed metal layer and the front-side metal layer are electrically connected through the via hole; a die attachment metal layer formed on a bottom surface of the diffusion barrier layer other than the via hole and an adjacent area near the via hole. The diffusion barrier layer prevents the backside metal layer from diffusing into the die attachment metal layer.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 28, 2019
    Inventors: Chang-Hwang HUA, Shu Chen CHEN, Huang-Wen WANG, Walter Tony WOHLMUTH
  • Publication number: 20190024115
    Abstract: The present invention relates to a transgenic pig in which an immune rejection response is suppressed during xenotransplantation, wherein a gene coding for heme oxygenase-1 (HO-1) and a gene coding for tumor necrosis factor receptor 1-Fc (TNFR1-Fc) are simultaneously expressed and a gene coding for ?-1,3-galactosyltransferase (GGTA1) is knocked out; and a method for producing the same. The transgenic pig of the present invention, in which the genes coding for human HO-1 and TNFR1-Fc fusion protein are simultaneously expressed and the gene coding for GGTA1 is knocked out, may reduce oxidative stress during organ isolation and in vitro culture by antioxidative reaction, cytoprotective function, etc., and may also reduce a TNF-?-mediated inflammatory response in early transplantation by TNFR1-Fc expression.
    Type: Application
    Filed: November 11, 2016
    Publication date: January 24, 2019
    Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, CHONG KUN DANG PHARMACEUTICAL CORP.
    Inventors: Byeong Chun Lee, Cu Rie Ahn, Geon A Kim, Su Cheong Yeom, Su Jin Kim, Bum Rae Cho, Eun Mi Lee, Sang Hoon Lee, In Chang Hwang, Hye Jin Hong
  • Publication number: 20180366913
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer, at least one stress balance layer and a die attachment layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein the at least one stress balance layer is made of at least one conductive material; the die attachment layer is formed on a bottom surface of the at least one stress balance layer, wherein the die attachment layer is made of conductive material. By locating the at least one stress balance layer between the contact metal layer and the die attachment layer, the stress suffered by the compound semiconductor wafer is balanced so that the distortion of the compound semiconductor wafer is reduced.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 20, 2018
    Inventors: Chang-Hwang HUA, Wen CHU
  • Publication number: 20180366418
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.
    Type: Application
    Filed: April 25, 2018
    Publication date: December 20, 2018
    Inventors: Chang-Hwang HUA, Wen CHU
  • Publication number: 20180366417
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer formed on a bottom surface of a compound semiconductor wafer, at least one stress balance layer formed on a bottom surface of the contact metal layer and made of nonconductive material, stress balance layer via holes and a die attachment layer. Each stress balance layer via hole penetrates the stress balance layer. The die attachment layer is made of conductive material, formed on a bottom surface of the stress balance layer and an inner surface of each stress balance layer via hole, and electrically connected with the contact metal layer through the stress balance layer via holes. By locating the stress balance layer between the contact metal layer and the die attachment layer, the stress suffered by the compound semiconductor wafer is balanced so that the distortion of the compound semiconductor wafer is reduced.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 20, 2018
    Inventors: Chang-Hwang HUA, Wen CHU
  • Patent number: 10158212
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer, at least one stress balance layer and a die attachment layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein the at least one stress balance layer is made of at least one conductive material; the die attachment layer is formed on a bottom surface of the at least one stress balance layer, wherein the die attachment layer is made of conductive material. By locating the at least one stress balance layer between the contact metal layer and the die attachment layer, the stress suffered by the compound semiconductor wafer is balanced so that the distortion of the compound semiconductor wafer is reduced.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: December 18, 2018
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Wen Chu
  • Patent number: 10146985
    Abstract: A sensing read-out circuit includes an amplifier circuit that converts a charge output from a sensing line of a sensor into a first voltage, another amplifier circuit that converts a charge output from another sensing line into a second voltage, another amplifier circuit that generates a first amplified voltage by amplifying a difference between the first voltage and the second voltage, an analog-to-digital converter that converts the first amplified voltage into a digital signal, a first mixer that generates a second mixed signal by mixing the first digital signal and an in-phase clock signal, a second mixer that generates a second mixed signal by mixing the first digital signal and a quadrature-phase clock signal, a first filter that generates an in-phase signal by performing low-pass filtering on the first mixed signal, and a second filter that generates a quadrature-phase signal by performing low-pass filtering on the second mixed signal.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae Young Chung, Jae Jin Park, Hee Chang Hwang
  • Patent number: 10096583
    Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 9, 2018
    Assignee: WIN Semiconductos Corp.
    Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Cheng-Kuo Lin, Chang-Hwang Hua
  • Publication number: 20180039809
    Abstract: A sensing read-out circuit includes an amplifier circuit that converts a charge output from a sensing line of a sensor into a first voltage, another amplifier circuit that converts a charge output from another sensing line into a second voltage, another amplifier circuit that generates a first amplified voltage by amplifying a difference between the first voltage and the second voltage, an analog-to-digital converter that converts the first amplified voltage into a digital signal, a first mixer that generates a second mixed signal by mixing the first digital signal and an in-phase clock signal, a second mixer that generates a second mixed signal by mixing the first digital signal and a quadrature-phase clock signal, a first filter that generates an in-phase signal by performing low-pass filtering on the first mixed signal, and a second filter that generates a quadrature-phase signal by performing low-pass filtering on the second mixed signal.
    Type: Application
    Filed: February 21, 2017
    Publication date: February 8, 2018
    Inventors: DAE YOUNG CHUNG, Jae Jin Park, Hee Chang Hwang
  • Publication number: 20180039810
    Abstract: A semiconductor device comprising a fingerprint sensor configured to generate first-direction sensing data and second-direction sensing data by sensing a fingerprint image in a first direction and a second direction, respectively, which is perpendicular to the first direction; a differential sensing circuit configured to generate first-direction first differential data and second-direction first differential data by performing a differential operation on the first-direction sensing data and the second-direction sensing data, respectively; and a fingerprint processing circuit configured to generate first-direction second differential data and second-direction second differential data by performing a differential operation on the first-direction first differential data and the second-direction first differential data, respectively, and generate fingerprint data by adding the first-direction second differential data and the second-direction second differential data.
    Type: Application
    Filed: July 12, 2017
    Publication date: February 8, 2018
    Inventors: Hee Chang HWANG, Jae Jin PARK, Min Chul LEE, Seung Hoon LEE, Dae Young CHUNG
  • Publication number: 20180012069
    Abstract: At least some example embodiments provide a fingerprint sensor, a fingerprint sensor package, and a fingerprint sensing system using light sources of a display panel. The fingerprint sensor includes an image sensor including a plurality of sensor pixels, the sensor pixels configured to sense light reflected by a fingerprint and generate image information corresponding to the fingerprint and a pinhole mask defining a plurality of pinholes, wherein each of the pinholes forms a focus for transmitting the light reflected by the fingerprint to the image sensor, wherein light is emitted from a plurality of organic light-emitting diodes (OLEDs) and is reflected by the fingerprint.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 11, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-young Chung, Hee-chang Hwang, Kun-yong Yoon, Woon-bae Kim, Bum-suk Kim, Min Jang, Min-chul Lee, Jung-woo Kim