Patents by Inventor Isamu Nishimura
Isamu Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210233700Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
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Patent number: 11011297Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: GrantFiled: February 27, 2020Date of Patent: May 18, 2021Assignee: ROHM CO., LTD.Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
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Patent number: 10985083Abstract: A semiconductor device includes a semiconductor element, a wiring portion, an electrode pad, a sealing resin and a heat dissipation layer. The semiconductor element has a front surface and a back surface opposite to the front surface in a thickness direction of the semiconductor device. The wiring portion is electrically connected to the semiconductor element. The electrode pad is electrically connected to the wiring portion. The sealing resin covers the semiconductor element. The heat dissipation layer is held in contact with the back surface of the semiconductor element and exposed from the sealing resin. The semiconductor element overlaps with the first heat dissipation layer as viewed in the thickness direction.Type: GrantFiled: February 7, 2019Date of Patent: April 20, 2021Assignee: ROHM CO., LTDInventor: Isamu Nishimura
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Patent number: 10930574Abstract: A semiconductor device includes a semiconductor element, a first substrate, a first electrode, a second electrode and a sealing resin. The first substrate has a first front surface and a first back surface that are spaced apart from each other in a thickness direction. The semiconductor element is mounted on the first main surface. The first electrode includes a first conductive portion and a second conductive portion. The first conductive portion is formed on a portion of the first front surface. The second conductive portion is connected to the first conductive portion and overlaps with the first substrate as viewed in a first direction perpendicular to the thickness direction. The sealing resin covers the semiconductor element. The second electrode is exposed from the sealing resin and electrically connected to the first electrode. The second electrode is in contact with the second conductive portion.Type: GrantFiled: April 25, 2019Date of Patent: February 23, 2021Assignee: ROHM CO., LTD.Inventor: Isamu Nishimura
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Publication number: 20200411425Abstract: A semiconductor device includes: a substrate including a main surface; a wiring portion including a first conductive layer formed on the main surface, and a first plating layer which is provided on the first conductive layer and on which an oxide film is formed; a semiconductor element including an element mounting surface and an element electrode formed on the element mounting surface; a bonding portion including a second plating layer made of the same material as the first plating layer and laminated on the first conductive layer, and a solder layer laminated on the second plating layer and bonded to the element electrode; and a sealing resin covering the semiconductor element.Type: ApplicationFiled: June 5, 2020Publication date: December 31, 2020Inventors: Isamu NISHIMURA, Hirofumi TAKEDA, Hideaki YANAGIDA, Taro HAYASHI, Natsuki SAKAMOTO
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Publication number: 20200391517Abstract: A thermal print head includes: a substrate; a resistor layer supported by the substrate and including a plurality of heat generating portions arranged in a main scanning direction; a wiring layer supported by the substrate and forming an energizing path to the plurality of heat generating portions; and an insulating layer interposed between the substrate and the resistor layer, wherein the substrate has a cavity portion overlapping the plurality of heat generating portions when viewed in a thickness direction of the substrate.Type: ApplicationFiled: June 11, 2020Publication date: December 17, 2020Inventor: Isamu NISHIMURA
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Publication number: 20200266172Abstract: A semiconductor device, includes: a semiconductor element including an element main surface and an element back surface facing opposite sides in a thickness direction; a wiring part electrically connected to the semiconductor element; an electrode pad electrically connected to the wiring part; a sealing resin configured to cover a part of the semiconductor element; and a first metal layer configured to make contact with the element back surface and exposed from the sealing resin, wherein the semiconductor element overlaps the first metal layer when viewed in the thickness direction.Type: ApplicationFiled: December 4, 2019Publication date: August 20, 2020Inventor: Isamu NISHIMURA
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Publication number: 20200203058Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: February 27, 2020Publication date: June 25, 2020Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
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Publication number: 20200176428Abstract: A semiconductor device includes a substrate having a main surface, a plurality of first wirings, each having a first embedded part embedded in the substrate and exposed from the main surface, and a mounted part which is in contact with the main surface and is connected to the first embedded part, a semiconductor element having an element rear surface and a plurality of electrodes bonded to the mounted parts, a plurality of second wirings, each having a second embedded part embedded in the substrate and exposed from the main surface and a columnar part protruding from the second embedded part in the thickness direction, and being located outward from the semiconductor element as viewed in the thickness direction; and a passive element located on the side facing the main surface in the thickness direction more than the semiconductor element, and electrically connected to the plurality of second wirings.Type: ApplicationFiled: November 26, 2019Publication date: June 4, 2020Inventors: Isamu NISHIMURA, Mamoru YAMAGAMI
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Patent number: 10651374Abstract: A semiconductor device includes a substrate having a front surface and a mounting surface that are separate from each other in a thickness direction. The substrate is formed with a through-hole that penetrates through in the thickness direction. A semiconductor element is mounted on the front surface of the substrate, and a front-surface wire line is formed on the front surface of the substrate to be electrically connected to the semiconductor element. A column is provided inside the through-hole, and is electrically connected to the front-surface wiring line. An electrode pad is provided on the mounting surface of the substrate, and is electrically connected to the column. A resin-layer through portion is also provided inside the through-hole. The semiconductor element is covered with a sealing resin. The resin-layer through portion has an orthogonal surface in contact with the column. The orthogonal surface is orthogonal to the mounting surface.Type: GrantFiled: December 3, 2018Date of Patent: May 12, 2020Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Hirofumi Takeda
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Publication number: 20190341323Abstract: A semiconductor device includes a semiconductor element, a first substrate, a first electrode, a second electrode and a sealing resin. The first substrate has a first front surface and a first back surface that are spaced apart from each other in a thickness direction. The semiconductor element is mounted on the first main surface. The first electrode includes a first conductive portion and a second conductive portion. The first conductive portion is formed on a portion of the first front surface. The second conductive portion is connected to the first conductive portion and overlaps with the first substrate as viewed in a first direction perpendicular to the thickness direction. The sealing resin covers the semiconductor element. The second electrode is exposed from the sealing resin and electrically connected to the first electrode. The second electrode is in contact with the second conductive portion.Type: ApplicationFiled: April 25, 2019Publication date: November 7, 2019Inventor: Isamu Nishimura
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Patent number: 10470310Abstract: An electronic component includes a first functional element including a pair of first connecting electrode portions formed on a first mounting surface, a pair of pillar electrodes connected to the corresponding first connecting electrode portions, a second functional element that includes a pair of second connecting electrode portions formed on a second mounting surface and that is arranged in a space defined by the first mounting surface of the first functional element and the pair of pillar electrodes, a pair of pad electrodes connected to the corresponding second connecting electrode portions, and a sealing resin that seals the pair of pillar electrodes, the pair of pad electrodes and the second functional element so as to expose the first lower surfaces of the pair of pillar electrodes and the second lower surfaces of the pair of pad electrodes.Type: GrantFiled: March 21, 2017Date of Patent: November 5, 2019Assignee: ROHM CO., LTD.Inventor: Isamu Nishimura
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Patent number: 10410944Abstract: The present disclosure provides a semiconductor device for high efficiently releasing heat generated from a semiconductor element to the outside.Type: GrantFiled: May 3, 2018Date of Patent: September 10, 2019Assignee: ROHM CO., LTD.Inventor: Isamu Nishimura
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Publication number: 20190252290Abstract: A semiconductor device includes a semiconductor element, a wiring portion, an electrode pad, a sealing resin and a heat dissipation layer. The semiconductor element has a front surface and a back surface opposite to the front surface in a thickness direction of the semiconductor device. The wiring portion is electrically connected to the semiconductor element. The electrode pad is electrically connected to the wiring portion. The sealing resin covers the semiconductor element. The heat dissipation layer is held in contact with the back surface of the semiconductor element and exposed from the sealing resin. The semiconductor element overlaps with the first heat dissipation layer as viewed in the thickness direction.Type: ApplicationFiled: February 7, 2019Publication date: August 15, 2019Inventor: Isamu Nishimura
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Publication number: 20190214555Abstract: A semiconductor device includes a substrate having a front surface and a mounting surface that are separate from each other in a thickness direction. The substrate is formed with a through-hole that penetrates through in the thickness direction. A semiconductor element is mounted on the front surface of the substrate, and a front-surface wire line is formed on the front surface of the substrate to be electrically connected to the semiconductor element. A column is provided inside the through-hole, and is electrically connected to the front-surface wiring line. An electrode pad is provided on the mounting surface of the substrate, and is electrically connected to the column. A resin-layer through portion is also provided inside the through-hole. The semiconductor element is covered with a sealing resin. The resin-layer through portion has an orthogonal surface in contact with the column. The orthogonal surface is orthogonal to the mounting surface.Type: ApplicationFiled: December 3, 2018Publication date: July 11, 2019Applicant: ROHM CO., LTD.Inventors: Isamu NISHIMURA, Hirofumi TAKEDA
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Patent number: 10347550Abstract: The present disclosure provides a semiconductor device and a method of making the same for suppressing warpages of an article due to a difference of temperature strains during the process of making the semiconductor device. The semiconductor device of the present disclosure includes a substrate having a main surface and a recess recessed therefrom; a semiconductor element disposed in the recess; a wiring portion connected to the substrate and electrically connected to the semiconductor element; and a sealing resin filled in the recess. The substrate includes an electrical insulative synthetic resin. The recess has a bottom surface and a connecting surface connected to the bottom surface and the main surface. The connecting surface includes a first inclined surface connected to the bottom surface; a second inclined surface connected to the main surface; and an intermediate surface connected to the first inclined surface and the second inclined surface.Type: GrantFiled: August 25, 2017Date of Patent: July 9, 2019Assignee: ROHM CO., LTD.Inventor: Isamu Nishimura
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Patent number: 10279597Abstract: A thermal print head includes a semiconductor substrate, a resistor layer with heat generating portions arranged in the main scanning direction, a wiring layer included in a conduction path for energizing the heat generating portions, and a protective layer covering the resistor layer and the wiring layer. The semiconductor substrate includes a projection protruding from the obverse surface of the substrate and elongated in the main scanning direction. The projection has first and second inclined side surfaces spaced apart from each other in the sub-scanning direction. The heat generating portions are arranged to overlap with the first inclined side surface of the projection as viewed in plan view.Type: GrantFiled: September 20, 2017Date of Patent: May 7, 2019Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Yasuhiro Fuwa
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Patent number: 10141500Abstract: A magnetoelectric converting element includes a substrate, a magnetosensitive layer, a first insulating layer, an underlying conductive layer, a second insulating layer, and a terminal conductor. The magnetosensitive layer is formed on the substrate. The first insulating layer is formed with first opening for exposing a part of the magnetosensitive layer. The underlying conductive layer is formed on the exposed part of the magnetosensitive layer. The second insulating layer is formed with a second opening for exposing a part of the underlying conductive layer. The terminal conductor is formed on the exposed part of the underlying conductive layer. The second opening is arranged to be located inside the first opening in plan view.Type: GrantFiled: July 3, 2017Date of Patent: November 27, 2018Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Michihiko Mifuji, Satoshi Nakagawa
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Publication number: 20180331008Abstract: The present disclosure provides a semiconductor device for high efficiently releasing heat generated from a semiconductor element to the outside.Type: ApplicationFiled: May 3, 2018Publication date: November 15, 2018Inventor: Isamu NISHIMURA
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Patent number: 10115651Abstract: An electronic component includes a substrate that has a first principal surface and a second principal surface, a chip that includes a mounting surface on which a plurality of terminal electrodes are formed and a non-mounting surface positioned on a side opposite to the mounting surface and that is arranged at the first principal surface of the substrate in a posture in which the mounting surface faces the first principal surface of the substrate, and a sealing resin that seals the chip at the first principal surface of the substrate so as to expose the non-mounting surface of the chip.Type: GrantFiled: May 1, 2017Date of Patent: October 30, 2018Assignee: ROHM CO., LTD.Inventor: Isamu Nishimura