Abstract: An exemplary embodiment relates to a method of shallow trench isolation (STI) formation using amorphous carbon as a sacrificial polish stop layer. The method can include polishing a silicon dioxide layer located above a wafer, polishing portions of the silicon dioxide layer located in a field area and portions of an amorphous carbon layer located in an active area. Portions of the amorphous carbon layer are polished down to a hard polish stop layer. The method can also include ashing away residual amorphous carbon from the amorphous carbon layer.

Abstract: A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also include planarizing a surface of the interlayer dielectric.

Abstract: A system and method are provided for maintaining state synchronization between a primary device and a secondary device. The present method includes the steps of generating a sequence identifier in the primary device, attaching the sequence identifier to a message in the primary device, transmitting the message and the sequence identifier attached thereto to the secondary device, and storing the sequence identifier in the secondary device as a secondary sequence identifier. In addition, the method includes the step of comparing a secondary sequence identifier from the secondary device with the sequence identifier in the primary device to detect a lost message.

Abstract: The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.

Abstract: A method of using amorphous carbon as spacer material in a disposable spacer process can include forming amorphous carbon spacers at lateral side walls of a gate structure over a substrate, implanting dopants in the substrate to form source and drain regions, ashing away the amorphous carbon spacers, and implanting dopants to form shallow structures in the substrate.

Abstract: A roller cone drill bit includes a bit body adapted to be rotated about a longitudinal axis. At least one leg which terminates in a shirttail portion depends from the bit body. The shirttail portion defines a first end face having a first circumferential groove thereon. The first circumferential groove has a radius equal to the radius of a tip of the shirttail portion. A journal is cantilevered from the leg, and a roller cone is rotatably mounted on the journal. The roller cone has a second end face adjacent to the first end face. A second circumferential groove is formed on the second end face.

Abstract: This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films.

Abstract: Strong adhesion to doped low-k inter-layer dielectrics is provided by varying the composition of dopant near the surface layers of the inter-layer dielectric. The concentration of dopant is gradually increased from about zero atomic % at the interface between the inter-layer dielectric and semiconductor substrate to improve adhesion of the inter-layer dielectric to the semiconductor substrate. The concentration of dopant at the upper surface of the inter-layer dielectric is gradually decreased to about zero atomic % at the upper surface of the inter-layer dielectric film in order to improve adhesion of additional layers to the inter-layer dielectric.

Abstract: A two stage process useful for cetane upgrading of diesel fuels. More particularly, the invention relates to a process for selective naphthenic ring-opening utilizing an extremely low acidic distillate selective catalyst having highly dispersed Pt. The process is a two stage process wherein the first stage is a hydrotreating stage for removing sulfur from the feed and the second stage is the selective ring-opening stage.

Abstract: A method of re-working a semiconductor device having a defective copper damascene interconnect structure, including the steps of obtaining a semiconductor wafer having at least one defect in a copper damascene interconnect structure; placing the wafer in an electrolyte in an electrolytic cell such that the defective copper damascene interconnect structure forms an anode; applying electrical current to the wafer to remove from the wafer substantially all copper from the defective copper damascene interconnect structure; re-applying copper to the semiconductor wafer to form a copper damascene interconnect structure.

Abstract: A system and method are provided for maintaining a common consistent database in a primary device and in a secondary device. The method includes the steps of determining a need for a merger of a first database maintained in the primary device and a second database maintained in the secondary device, the first and second databases being derived from common database. The method also includes the steps of merging the first database and the second database, resulting in a merged database and assigning a sequence identifier to the merged database. Finally the present method includes the step of synchronizing the merged database in the primary and secondary devices.

Abstract: A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

Abstract: A semiconductor device formed on a substrate includes at least one metal stack formed on the substrate. A fluorosilicate glass layer is formed on the at least one metal stack, where the fluorosilicate glass layer acts as an interlayer dielectric for the semiconductor device. The fluorosilicate glass layer includes a fluorine-depleted layer at a top portion of the fluorosilicate glass layer that is further away from the substrate. The fluorine-depleted layer is formed by treating the fluorosilicate glass layer with a hydrogen plasma, such as an H2/N2 plasma. The fluorine-depleted layer lessens a likelihood of fluorine atoms in the fluorosilicate glass layer from moving into and thereby corrupting a conducting layer formed above the fluorosilicate glass layer.

Abstract: Insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. A corrosive dielectric material having low dielectric constant is deposited to surround the interconnect structures, and the corrosive dielectric material fills any gaps between the interconnect structures. Deposition of the corrosive dielectric material is performed within the reaction chamber, and the corrosive dielectric material is deposited on the reaction chamber during deposition of the corrosive dielectric material on the first semiconductor wafer.

Abstract: A cutter element for use in a drill bit, comprising a substrate and a cutting layer. The substrate comprises a grip portion and an extension portion, where the grip portion has an insert axis and an extension portion including an interface surface having a first apex. The cutting layer is affixed to the interface surface and has a cutting surface having a second apex. The cutting layer is shaped such that when a plane passing through the first apex and lying parallel to the insert axis and normal to a radius from the insert axis, the plane divides the cutting layer into major and minor portions and the major portion has a major volume that is at least 60 percent of the total volume of said cutting layer. Alternative embodiments of the present invention include variations wherein the first and second apices do not coincide and wherein the interface surface of the substrate is not axisymmetric. Using these variations, cutter elements having sizeable variations in thickness are constructed.

Abstract: A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.

Abstract: A retroreflective article 10 has a body portion 14 and a multitude of cube-corner elements 12 that project from a rear side 20 of the body portion 14. The body portion 14 includes a body layer 18 that contains a light-transmissible polymeric material having an elastic modulus less than 7×108 pascals. The cube-corner elements 12 contain a light transmissible polymeric material having an elastic modulus greater than 16×108 pascals. A retroreflective article of this construction can be highly flexed while maintaining good retroreflective performance.

Abstract: A pack of self-opening bags with a front, rear, and co-joined side walls, with front and rear tabs extending from top edges of the front and rear walls. The tabs have a curved aperture slits therein, and the tabs are frangibly adhered together with contact adhesive. The slit has a main cut section, a first curved end section at one end, and a second curved end section at the opposite end. The first curved section has a curve that extends upwardly and inwardly from the main cut section. The second curved section has a substantially semi-circular curve that extends from the main cut section in a direction towards the bottom edge of the tab and has an end that is substantially perpendicular to and adjacent the main cut section. In one embodiment, the first curved section is dashed.

Abstract: A two stage process useful for cetane upgrading of diesel fuels. More particularly, the invention relates to a process for selective naphthenic ring-opening utilizing an extremely low acidic distillate selective catalyst having highly dispersed Pt. The process is a two stage process wherein the first stage is a hydrotreating stage for removing sulfur from the feed and the second stage is the selective ring-opening stage.

Abstract: A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.