Patents by Inventor J. Huang

J. Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes
    Patent number: 7183198
    Abstract: A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: February 27, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pei-Yuan Gao, Lu You, Richard J. Huang
  • Method of using carbon spacers for critical dimension (CD) reduction
    Patent number: 7169711
    Abstract: A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: January 30, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Philip A. Fisher, Richard J. Huang, Cyrus E. Tabery
  • Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit
    Patent number: 7141502
    Abstract: A method for Chemical-Mechanical Polishing utilizes a two step process. The first step utilizes a slurry with abrasive particles which become embedded into a conditioned polishing pad having small cavities in the surface. During the second step the slurry flow is discontinued and the final polishing is performed using the embedded small abrasive particles. Using this method dishing has been reduced considerably, and has enabled the fabrication of a Damascene metal gate NMOSFET fabricated with Atomic Layer Deposition (ALD).
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: November 28, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James J. Xie, Kashmir S. Sahota, Richard J. Huang
  • Method of forming an interlevel dielectric layer employing dielectric etch-back process without extra mask set
    Patent number: 7132306
    Abstract: A method of forming an interlevel dielectric (ILD) layer forms a polymer sacrificial ILD on a substrate. After metallization structures are formed in the polymer sacrificial ILD layer, a low power etch back is performed on the sacrificial ILD layer. Dielectric material is non-conformally deposited as an ILD layer over the substrate and the metallization structures, forming air gaps between some of the metallization structures.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: November 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seung-Hyun Rhee, Richard J. Huang, Calvin T. Gabriel
  • Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon
    Patent number: 7084071
    Abstract: A method of producing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate and providing an amorphous carbon layer over the polysilicon material layer. The amorphous carbon layer comprises at least one undoped amorphous carbon layer and at least one doped amorphous carbon layer. A portion of the amorphous carbon layer is removed to form a hard mask, and the polysilicon material layer is etched according to the hard mask to form a line of polysilicon material.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: August 1, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Scott A. Bell, Richard J. Huang, Richard C. Nguyen, Cyrus E. Tabery
  • Use of amorphous carbon for gate patterning
    Patent number: 7015124
    Abstract: A method of producing an integrated circuit includes providing a mask definition structure above a layer of conductive material and providing a mask above the layer of conductive material and in contact with at least a portion of the mask definition structure. The mask definition structure comprises a first material and the mask comprises a second material, wherein at least one of the first and second materials comprises amorphous carbon. The mask definition structure is removed, and the layer of conductive material is patterned according to the mask.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: March 21, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Philip A. Fisher, Richard J. Huang, Cyrus E. Tabery
  • Blue-light generating femtosecond wavelength-tunable non-collinear optical parametric amplifier
    Publication number: 20060044642
    Abstract: The present invention discloses a means of the generation of tunable femtosecond pulses from 380 nm to 465 nm near the degenerate point of a 405-nm pumped type-I BBO non-collinearly phase-matched optical parametric amplifier (NOPA). The tunable UV/blue radiation is obtained from sum frequency generation (SFG) between the OPA output and the residual fundamental beam at 810-nm and cascaded second harmonic generation (SHG) of OPA. With a pumping energy of 75 mJ at 405 nm, the optical conversion efficiency from the pump to the tunable SFG is more than 5% and the efficiency of SHG of the OPA is about 2%.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 2, 2006
    Inventors: Ci-Ling Pan, J. Huang, Jing-Yuan Zhang, Chao-Kuei Lee
  • Semiconductor component and method of manufacture
    Patent number: 6927113
    Abstract: A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask and into the dielectric layer. The opening is lined with a barrier layer and filled with an electrically conductive material. The electrically conductive material is planarized, where the planarization process stops on the barrier layer. Following planarization, the electrically conductive material is recessed using either an over-polishing process with highly selective copper slurry or a wet etching process to partially re-open the filled metal-filled trench or via. The recess process is performed such that the exposed portion of the electrically conductive material is below the dielectric layer.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: August 9, 2005
    Assignee: Advanced Micro Devices
    Inventors: Kashmir S. Sahota, Jeremy Martin, Richard J. Huang, James J. Xie
  • Methods and apparatus for use in aiding stack unwinding
    Patent number: 6892379
    Abstract: In a compiler, a method of generating assembly code for stack unwinding is disclosed. One or more source code lines are obtained. Assembly code for the one or more source code lines is then generated. The assembly code includes one or more stack unwind assembler having one or more associated stack unwind sub directives. Each of the stack unwind assembler directives is adapted for indicating to an assembler that one or more encoded data sections containing stack information to be used for stack unwinding is to be generated in an object file from the one or more associated stack unwind sub directives.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: May 10, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Alfred J. Huang
  • Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and ARC material
    Patent number: 6875664
    Abstract: A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region is formed intermediate the amorphous carbon material layer and the ARC material layer. The transition region has a concentration profile that provides a transition between the amorphous carbon material layer and the ARC material layer. A portion of the amorphous carbon material layer, the ARC material layer, and the transition region is removed to form a hard mask, and a feature is formed in the layer of conductive material according to the hard mask.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: April 5, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Huang, Srikanteswara Dakshina-Murthy, Philip A. Fisher, Cyrus E. Tabery, Lu You
  • EUV reflective mask having a carbon film and a method of making such a mask
    Patent number: 6869734
    Abstract: An exemplary embodiment relates to a mask for integrated circuit fabrication equipment. The mask includes a multilayer film and an amorphous carbon layer above the multilayer film. The multilayer film is at least partially relatively reflective to radiation having a wavelength of less than 70 nanometers.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: March 22, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Cyrus E. Tabery, Richard J. Huang
  • CVD organic polymer film for advanced gate patterning
    Patent number: 6864556
    Abstract: A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 8, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lu You, Marina V. Plat, Chih Yuh Yang, Scott A. Bell, Richard J. Huang, Christopher F. Lyons, Mark S. Chang, Marilyn I. Wright
  • Method of using amorphous carbon to prevent resist poisoning
    Patent number: 6855627
    Abstract: An exemplary embodiment relates to a method of using an amorphous carbon layer to prevent photoresist poisoning. The method includes doping a first amorphous carbon layer located above a substrate, providing an oxide layer above the first amorphous carbon layer where the oxide layer has a pinhole, and providing a second amorphous carbon layer adjacent to the oxide layer. The second amorphous carbon layer is undoped and the second amorphous carbon layer helps prevent photoresist poisoning.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: February 15, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Scott A. Bell, Richard J. Huang, Richard C. Nguyen, Cyrus E. Tabery
  • Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration
    Patent number: 6831003
    Abstract: For filling an interconnect opening within a porous dielectric material, a diffusion barrier material is deposited onto at least one sidewall of the interconnect opening. A thickness of the diffusion barrier material is equal to or greater than a radius of a pore opened at the sidewall to substantially fill the opened pore. The thickness of the diffusion barrier material is equal to or greater than a mean radius of pores opened at the sidewall to substantially fill a majority of the opened pores. Or, the thickness of the diffusion barrier material is equal to or greater than a radius of a largest pore opened at the sidewall to substantially fill all opened pores. The interconnect opening is then filled with a conductive fill material.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: December 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Huang, Pin-Chin C. Wang, Darrell M. Erb
  • Methods and apparatus for use in aiding stack unwinding
    Publication number: 20040205741
    Abstract: In a compiler, a method of generating assembly code for stack unwinding is disclosed. One or more source code lines are obtained. Assembly code for the one or more source code lines is then generated. The assembly code includes one or more stack unwind assembler having one or more associated stack unwind sub directives. Each of the stack unwind assembler directives is adapted for indicating to an assembler that one or more encoded data sections containing stack information to be used for stack unwinding is to be generated in an object file from the one or more associated stack unwind sub directives.
    Type: Application
    Filed: June 20, 2001
    Publication date: October 14, 2004
    Inventor: Alfred J. Huang
  • Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes
    Patent number: 6803313
    Abstract: A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: October 12, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pei-Yuan Gao, Lu You, Richard J. Huang
  • METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT HAVING A BARRIER-LINED OPENING
    Publication number: 20040175926
    Abstract: A semiconductor component having a metallization system that includes a thin conformal multi-layer barrier structure and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a lower level interconnect. A hardmask is formed over the dielectric layer and an opening is etched through the hardmask into the dielectric layer. The opening is lined with a thin conformal multi-layer barrier using atomic layer deposition. The multi-layer barrier lined opening is filled with an electrically conductive material which is planarized.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 9, 2004
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Pin-Chin Connie Wang, Richard J. Huang
  • Cu damascene interconnections using barrier/capping layer
    Patent number: 6689684
    Abstract: Interconnects to an underlying Cu feature are formed with improved reliability by replacing a portion of the capping layer in the bottom of an opening in an overlying dielectric layer, e.g., an ILD, with a barrier material, such as Ta or TaN. During Ar sputter etching to round the ILD corners, the exposed barrier layer portion is removed and redeposited to form a liner on the side surfaces of the dielectric layer defining the opening, thereby avoiding Cu redeposition on, and/or penetration through, the side surfaces of the dielectric layer.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: February 10, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lu You, Fei Wang, Richard J. Huang
  • Use of diamond as a hard mask material
    Patent number: 6673684
    Abstract: A method for producing an integrated circuit includes providing a diamond layer above a layer of conductive material. A cap layer is provided above the diamond layer and patterned to form a cap feature. The diamond layer is patterned according to the cap feature to form a mask, and at least a portion of the layer of conductive material is removed according to the mask.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: January 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Huang, Philip A. Fisher, Cyrus E. Tabery
  • Method of shallow trench isolation (STI) formation using amorphous carbon
    Patent number: 6653202
    Abstract: An exemplary embodiment relates to a method of shallow trench isolation (STI) formation using amorphous carbon as a sacrificial polish stop layer. The method can include polishing a silicon dioxide layer located above a wafer, polishing portions of the silicon dioxide layer located in a field area and portions of an amorphous carbon layer located in an active area. Portions of the amorphous carbon layer are polished down to a hard polish stop layer. The method can also include ashing away residual amorphous carbon from the amorphous carbon layer.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: November 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Philip A. Fisher, Richard J. Huang