Abstract: An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vapor deposition equipment, subject to chemical-mechanical polishing, and then processed by a conventional photolithographic process for depositing conductors. The material is then reprocessed for each successive layer of conductor separated by dielectric.

Abstract: In connection with an electronic reading/annotation device, a method for automatically selecting between an electronic writing pen tool used for handwriting tasks and an electronic marker tool used for highlighting tasks is provided. Whereas handwriting normally consists of small radius curves, and frequent changes of direction, highlighting strokes are normally long and smooth with hardly ever a change of direction. The automatic selection method utilizes analysis of the shape of each stroke. More specifically, the length of each stroke is calculated between a starting point and a later made point of the stroke. If the length of the stroke is close to that of a straight line between the same two points and the stroke is determined not to be a handwriting stroke, the highlighting function is automatically selected. The exact determination of “close” is a tunable parameter.

Abstract: A hydrocracking catalyst is provided that includes a crystalline molecular sieve material component having a faujasite structure and an alpha acidity of less than 1, preferably 0.3 or less, and a dispersed Group VIII noble metal component. The extremely low acidity allows selective hydrocracking of the aromatic and naphthenic species in a feedstock, while limiting the cracking of paraffins. The catalyst produces improved yields of products, such as diesel fuel, at high conversion rates and with high cetane values.

Abstract: The invention provides a system and a method for densifying a surface of a porous film. By reducing the porosity of a film, the method yields a densified film that is more impenetrable to subsequent liquid processes. The method comprises the steps of providing a film having an exposed surface. The film can be supported by a semiconductor substrate. When the film is moved to a processing position, a focused source of radiation is created by a beam source. The exposed surface of the film is then irradiated by the beam source at the processing position until a predetermined dielectric constant is achieved. The film or beam source may be rotated, inclined, and/or moved between a variety of positions to ensure that the exposed surface of the film is irradiated evenly.

Abstract: Composite constructions of this invention comprise an ordered microstructure made up of multiple structural units that can be the same or different, and that comprise at least a first structural phase and a second structural phase. The first structural phase comprises a hard material that is selected from the group consisting of cermet materials, PCD, PCBN and mixtures thereof. The second structural phase is in contact with the first phase and comprises a material that is different than that selected to form the first structural phase. Additionally, the second structural phase is in contact with at least a portion of the first structural phase. Composite constructions of this invention can also have a multi-layer structures comprising two or more layers, wherein at least one of the layers comprises a composite construction having an ordered microstructure made up of the multiple structural units described above.

Abstract: A thermally grown oxide buffer layer is formed on a silicon layer prior to depositing an ARC thereon, thereby preventing damage to the silicon layer during ARC removal. Embodiments include thermally growing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by thermal oxidation at a temperature of about 800° C. to about 900° C. in an atmosphere comprising oxygen or steam. A silicon oxynitride or silicon-rich silicon nitride ARC is then formed on the thermally grown protective silicon oxide buffer layer and a photoresist layer is formed on the ARC. The photoresist layer is patterned to form a mask and the underlying silicon layer etched to form a conductive feature, e.g., gate electrode. The photoresist mask is then removed and the ARC is stripped with hot phosphoric acid or by dry etching, while the thermally grown silicon oxide buffer layer protects the underlying silicon layer from damage.

Abstract: An article is disclosed that has a patterned surface containing alternating hydrophobic and hydrophilic surface regions. The hydrophobic regions may be sufficiently narrow such that under dew conditions moisture accumulated on the hydrophobic region migrates to the hydrophilic region, thus preventing the accumulation of water droplets. In frost conditions, the hydrophobic region remains relatively frost-free, thus maintaining at least partial transparency of the surface. Inorganic oxide particles on the surfaces of the hydrophobic regions may provide abrasion resistance. A method for making the patterned surfaces is disclosed in which a treatment removes organic binder to expose inorganic oxide particles at the surface of the hydrophilic regions.

Abstract: A retroreflective article 10 has a body portion 14 and a multitude of cube-corner elements 12 that project from a rear side 20 of the body portion 14. The body portion 14 includes a body layer 18 that contains a light-transmissible polymeric material having an elastic modulus less than 7×108 pascals. The cube-corner elements 12 contain a light transmissible polymeric material having an elastic modulus greater than 16×108 pascals. A retroreflective article of this construction can be highly flexed while maintaining good retroreflective performance.

Abstract: A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.

Abstract: A cutter element for use in a drill bit, comprising a substrate and a plurality of layers thereon. The substrate comprises a grip portion and an extending portion. The layers are applied to the extending portion such that at least one of the layers is harder than at least one of the layers above it. The layers can include one or more layers of polycrystalline diamond and can include a layer in which the composition of the material changes with distance from the substrate.

Abstract: A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

Abstract: A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

Abstract: A semiconductor wafer includes a substrate, an aluminum layer on the substrate, an anti-reflection coating on the aluminum layer, a dielectric layer on the anti-reflection coating, and a via hole that passes through the dielectric layer and the anti-reflection coating down to a predetermined depth within the aluminum layer. A titanium layer is formed on the bottom and on the walls of the via hole. A physical vapor deposition process is then performed to form a first titanium nitride layer on the titanium layer. A chemical vapor deposition process is then performed to form a second titanium nitride layer on the first titanium nitride layer.

Abstract: Improved methods for manufacturing semiconductor devices incorporating barrier layers at metal/dielectric interfaces include the use of nitrogen-rich plasma, ion beam implantation and/or electromagnetic radiation to form regions of nitrided metal. The barrier layers decrease the diffusion of dopants such as fluorine, phosphorous and boron from the dielectric material into the metal, thereby decreasing the formation of metal salts. By decreasing the formation of metal salts, the barrier layers of this invention decrease the formation of voids and areas of delamination, and thereby decrease the loss of electrical reliability during manufacture and during use. Additional aspects of this invention include methods for monitoring the deposition of thin metal films using sheet resistance measurements, and further embodiments of this invention include methods for monitoring the surface texture of films that undergo phase transitions.

Abstract: A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

Abstract: A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

Abstract: This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films.

Abstract: A process, preferably in a counter-current configuration, for selectively cracking carbon-carbon bonds of naphthenic species using a low acidic catalyst, preferably having a crystalline molecular sieve component and carrying a Group VIII noble metal. The diesel fuel products are higher in cetane number and diesel yield.

Abstract: This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films.

Abstract: An oxide buffer layer is formed between an underlying silicon layer and overlying ARC to prevent damage to the silicon layer when removing the ARC. Embodiments include depositing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by PCVD, LPCVD or high temperature CVD, forming a SiON or Si-rich SiN ARC on the silicon oxide buffer layer, forming a photoresist mask on the ARC, patterning the underlying silicon layer to form a conductive line or gate electrode, stripping the photoresist mask and then stripping the ARC with hot phosphoric acid while the silicon oxide buffer layer protects the underlying silicon feature from pitting.