Patents by Inventor J. Ireland

J. Ireland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160195581
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Patent number: 9347985
    Abstract: A via chain testing structure includes: a substrate; a dielectric layer disposed on the substrate; a first via chain disposed on dielectric layer; a second via chain, being disposed on the dielectric on both sides of the first via chain and in thermal proximity with the first via chain; a first heating source disposed under the substrate, for providing thermal heat to the first via chain; and an electrical current source for heating the second via chain so the second via chain acts as a second heating source for the first via chain.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: May 24, 2016
    Assignee: NANYA TECHNOLOGY CORP.
    Inventors: Philip J. Ireland, Wen-Sung Chiang
  • Patent number: 9345812
    Abstract: Medical tubing (T), such as a guidewire, a stent, a catheter or a hollow needle, made of a kinked rigid-rod polyarylene exhibiting a outstanding characteristics including high torqueability, high pushability and high flexibility and which can be easily thin-wall extruded under especially harsh conditions.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 24, 2016
    Assignee: SOLVAY SPECIALTY POLYMERS USA, LLC
    Inventors: Mohammad Jamal El-Hibri, Brian Baleno, Nikica Maljkovic, Bianca Sadicoff Shemper, Jean-Baptiste Bonnadier, Daniel J. Ireland, Henri N. J. Massilon
  • Patent number: 9343362
    Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Philip J. Ireland, Sarah A. Niroumand
  • Patent number: 9320979
    Abstract: A method and apparatus is shown to allow the creation of sound programmers and complementary sound decoders that may be securely downloaded with sound and IPL data and that will operate in power limited environments with resistance to power drop outs and are significant improvements beyond prior art devices.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: April 26, 2016
    Inventor: Anthony J Ireland
  • Patent number: 9287184
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Publication number: 20150170979
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Patent number: 9050539
    Abstract: A method and apparatus is shown to allow expanded control capability for devices on and attached to a model railroad layout. Included is the capability for track section occupancy detection for one or more track sections, employing a switched impedance occupancy detection method, simultaneously allowing; transponding location and/or data feedback detection and intelligent power management, and/or autoreversing methods in the same device, and further providing for this encoded detection and power state information to be communicated to a layout control and monitoring system. Additional capability is to display on the local device or remote indicator lights and/or aural alarms any user selectable device state information by employing a recognizable and predefined indication pattern.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 9, 2015
    Inventor: Anthony J. Ireland
  • Publication number: 20150130029
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Application
    Filed: October 3, 2014
    Publication date: May 14, 2015
    Inventors: Alan G. Wood, Philip J. Ireland
  • Publication number: 20150008171
    Abstract: The invention provides a high-performance liquid chromatography system, said system is controlled in temperature by running a fluid in sleeves that surround the different parts of the system. All parts in contact with the fluid are made in fluoropolymer, carbon-filled fluoropolymer, or carbon-fiber fluoropolymer.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 8, 2015
    Inventors: Nicolas Dauphas, Francois L.H. Tissot, Reika Yokochi, Thomas J. Ireland
  • Patent number: 8853072
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Philip J. Ireland
  • Publication number: 20140287584
    Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.
    Type: Application
    Filed: December 31, 2013
    Publication date: September 25, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Philip J. Ireland, Sarah A. Niroumand
  • Publication number: 20140236101
    Abstract: Medical tubing (T), such as a guidewire, a stent, a catheter or a hollow needle, made of a kinked rigid-rod polyarylene exhibiting a outstanding characteristics including high torqueability, high pushability and high flexibility and which can be easily thin-wall extruded under especially harsh conditions.
    Type: Application
    Filed: April 25, 2014
    Publication date: August 21, 2014
    Applicant: SOLVAY ADVANCED POLYMERS, L.L.C.
    Inventors: Mohammad Jamal EL-HIBRI, Brian BALENO, Nikica MALJKOVIC, Bianca Sadicoff SHEMPER, Jean-Baptiste BONNADIER, Daniel J. IRELAND, Henri N. J. MASSILON
  • Patent number: 8753981
    Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Philip J. Ireland, Sarah A. Niroumand
  • Patent number: 8742064
    Abstract: Medical tubing (T), such as a guidewire, a stent, a catheter or a hollow needle, made of a kinked rigid-rod polyarylene exhibiting a outstanding characteristics including high torqueability, high pushability and high flexibility and which can be easily thin-wall extruded under especially harsh conditions.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: June 3, 2014
    Assignee: Solvay Advanced Polymers, L.L.C.
    Inventors: Mohammad Jamal El-Hibri, Brian Baleno, Nikica Maljkovic, Bianca Sadicoff Shemper, Jean-Baptiste Bonnadier, Daniel J. Ireland, Henri N. J. Massillon
  • Patent number: 8680595
    Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Philip J. Ireland, Howard E. Rhodes
  • Patent number: 8569893
    Abstract: This document discusses, among other things, example systems including integrated circuit contacts configured to reduce the likelihood of shorting to unrelated portions of overlying conductive material due to contact misalignment.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: October 29, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Philip J. Ireland
  • Publication number: 20130228656
    Abstract: A method and apparatus is shown to allow expanded control capability on model railroad layouts. Also included is the capability to introduce occupancy detection, transponding or data feedback detection and intelligent power management, and autoreversing methods in the same device.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 5, 2013
    Inventor: Anthony J. Ireland
  • Patent number: 8482131
    Abstract: A via structure includes at least a first via set and a second via set electrically connected to the first via set. There is at least one via in the first via set and at least one via in the second via set. The via in the first via set has a cross-sectional area which is larger than that of the via in the second via set.
    Type: Grant
    Filed: July 31, 2011
    Date of Patent: July 9, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Philip J. Ireland
  • Patent number: 8410612
    Abstract: Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: April 2, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Philip J. Ireland