Abstract: Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer due to contact misalignment. Embodiments for forming the integrated circuit include performing a first etching process to pattern the conductive layer, where the etching compound used in the first etching process is relatively selective to the conductive layer's materials. Embodiments also include performing a second, contact related etching process that removes a portion of any misaligned contacts that were exposed by the first etching process, where the etching compound used in the second etching process is selective to the contacts' materials. The embodiments can be used to form vias and other interconnect structures as well. The modified contacts and vias are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: Polymer composition (C) comprising: at least one poly(aryl ether ketone) (P1), at least one poly(biphenyl ether sulfone) (P2), and at least one fibrous carbon nanofiller (N). Article or part of an article comprising the polymer composition (C).

Abstract: The present invention provides compositions and methods for regulating fertility in mammals. In general, the invention relates to a novel protein produced by oocytes named JY-1, and nucleic acids encoding the JY-1 protein, for controlling folliculogenesis and early embryonic development, particularly in monoovulatory species. In particular, the present invention provides nucleic acid and amino acid sequences encoding JY-1, vectors for the expression of JY-1, host cells expressing JY-1, RNAi probes for reducing levels of JY-1 message, and antibodies to JY-1. Specifically, developing and mature oocytes express JY-1 in vivo, while granulosa cells treated in vitro with recombinant JY-1 (rJY-1) protein reduced cell proliferation while increasing progesterone synthesis and estradiol production. Further, reducing JY-1 protein in developing embryos in vitro using inhibitory siRNA constructs corresponded with arrested blastocyte maturation.

Abstract: A method and apparatus is shown to allow expanded control capability of digital locomotives on model railroad layouts that also permit compatible speed and direction operation simultaneously for non-digital or conventional locomotives alongside. The improvements employ mixed-mode control encoding and decoding algorithms and methods that are expanded beyond the prior art for control mode changes used on model railroad layouts.

Abstract: A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers between a reflective surface and another material. The indices of refraction, absorptions, and thicknesses of the at least two anti-reflective coating layers are chosen such that the amplitudes and phase differences of radiation reflected from the anti-reflective coating layers, as well as any other reflective surfaces below the anti-reflective coating layers, mutually cancel when combined. The invention may be practiced using more than two layers of anti-reflective coating. Multiple layers of anti-reflective coating may be used below an inter-level dielectric, in which case they may serve the additional purpose of functioning as an etch-stop.

Abstract: A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectric is formed over these conductive structures, then a portion of the first dielectric layer is removed which forms a hole in the dielectric layer to expose the second conductive structure. Subsequently, the second conductive structure is removed to leave a void or tunnel in the dielectric layer where the second conductive structure had previously existed. Finally, a second dielectric layer is provided to fill the hole but to leave the void or tunnel in the dielectric layer subsequent to the formation of the second dielectric layer. An inventive structure resulting from the inventive method is also described.

Abstract: A middle ear prosthesis comprises a body of deformable material capable of retaining different shapes. The body comprises a slotted wall defining a cavity for receiving a bone of the middle ear. The wall is deformable proximate slots in the wall between an open position for receiving the bone and a closed position wherein the body is reshaped to grasp the bone.

Abstract: A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers between a reflective surface and another material. The indices of refraction, absorptions, and thicknesses of the at least two anti-reflective coating layers are chosen such that the amplitudes and phase differences of radiation reflected from the anti-reflective coating layers, as well as any other reflective surfaces below the anti-reflective coating layers, mutually cancel when combined. The invention may be practiced using more than two layers of anti-reflective coating. Multiple layers of anti-reflective coating may be used below an inter-level dielectric, in which case they may serve the additional purpose of functioning as an etch-stop.

Abstract: Techniques for generating deliverable files from well logging data include obtaining the well logging data, wherein the well logging data is associated with a unique identifier; outputting a graphical deliverable file based on the well logging data, one or more templates, and a set of graphical deliverable attributes that specify how the graphical deliverable file is to be generated; and outputting an electronic data file comprising the set of graphical deliverable attributes such that the graphical deliverable file can be regenerated from the electronic data file. The well logging data may include all information necessary to recalculate the computed outputs from the raw data (e.g., computational parameters). Other methods include techniques for uniquely associating data and for making the outputs tamper-proof so that a user can compare two different types of outputs (e.g., digital and graphical deliverables) and be confident whether they are from the same source data.

Abstract: A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.

Abstract: Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in reduced interconnect resistance, I2R losses, and defects or variations due to cusping. Embodiments of the methods involve forming an opening in an insulating layer, where the opening forms a trench that exposes an underlying portion of a metal layer. Additional embodiments involve depositing multiple layers of conductive material within the opening and above the insulating layer, where one of the conductive layers includes aluminum and is deposited using a “cold aluminum” process, and a second one of the conductive layers also includes aluminum, but is deposited using a “hot aluminum” process. The interconnect structures are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A lower bulk insulator layer, a capacitor dielectric layer, a cell plate conductor layer, and an upper bulk insulator layer are formed upon a semiconductor substrate. An etch removes the cell plate conductor layer, the capacitor dielectric layer, and the lower bulk insulator layer so as to form an opening terminating within the lower bulk insulator layer. A sleeve insulator layer is deposited upon the upper bulk insulator layer and within the opening. Another etch removes the sleeve insulator layer from the bottom surface within the lower bulk insulator layer. A still further etch creates a contact hole that exposes a contact. The contact can be upon a transistor gate, a capacitor storage node, or an active region on the semiconductor substrate.

Abstract: Titanium-containing films exhibiting excellent uniformity and step coverage are deposited on semiconductor wafers in a cold wall reactor which has been modified to discharge plasma into the reaction chamber. Titanium tetrabromide, titanium tetraiodide, or titanium tetrachloride, along with hydrogen, enter the reaction chamber and come in contact with a heated semiconductor wafer, thereby depositing a thin titanium-containing film on the wafer's surface. Step coverage and deposition rate are enhanced by the presence of the plasma. The use of titanium tetrabromide or titanium tetraiodide instead of titanium tetrachloride also increases the deposition rate and allows for a lower reaction temperature. Titanium silicide and titanium nitride can also be deposited by this method by varying the gas incorporated with the titanium precursors.

Abstract: A fill pattern for a semiconductor device. The device includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.

Abstract: A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectric is formed over these conductive structures, then a portion of the first dielectric layer is removed which forms a hole in the dielectric layer to expose the second conductive structure. Subsequently, the second conductive structure is removed to leave a void or tunnel in the dielectric layer where the second conductive structure had previously existed. Finally, a second dielectric layer is provided to fill the hole but to leave the void or tunnel in the dielectric layer subsequent to the formation of the second dielectric layer. An inventive structure resulting from the inventive method is also described.

Abstract: Embodiments of the invention concern modifying the layout of one or more metal layers of an integrated circuit before patterning those layers, so that an intermetal dielectric layer (IDL) subsequently deposited over the top surface of the patterned layer will be substantially self-planarized. The spacing between parallel edges of adjacent first metal lines and features is standardized, and one or more additional metal features are included in areas where an intersection exists. The additional metal features serve to maintain the elevation of the top surface of the IDL at the same height across the intersections, thus achieving self-planarization across the entire top surface of the IDL, without the need for a thicker than desired IDL. The modified metal layers are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A metal line layout which includes two separate control spaces to address capacitive issues along speed sensitive pathways in an integrated circuit structure without negatively impacting Werner Fill processing. One control space (i.e., DRCgap1) is for decreasing the spacing between various metal features to standardize such spacing, and a second control space (i.e., DRCgap2) is for addressing capacitance issues along speed sensitive pathways. Between speed sensitive pathways, spacing of added metal features provided to long parallel metal lines are maintained at the second control spacing DRCgap2. Spaces at the ends of such long parallel metal lines are reduced to the first control spacing DRCgap1 in order to best fill three-way-intersections (TWIs) with subsequent depositions.

Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. At least two opposing, contoured, merging dielectric surfaces define at least one elongated passageway which has at least one opening. A conductive material then substantially fills the at least one opening and at least one elongated passageway to form at least one electrical interconnect guided by the at least one elongated passageway and extended through the layer of dielectric material along the length to electrically connect at least two of the components of the integrated circuit.

Abstract: Disclosed is a circuit element that includes a thermoplastic substrate and a conductive trace at least partially embedded in the thermoplastic substrate. Also disclosed is a method of forming a circuit element. The method includes the steps of providing a thermoplastic substrate having a softening temperature, printing a conductive ink onto the thermoplastic substrate to form a trace, and embedding the trace into the thermoplastic substrate by heating the thermoplastic substrate to a temperature above about the softening temperature about the trace.

Abstract: Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer due to contact misalignment. Embodiments for forming the integrated circuit include performing a first etching process to pattern the conductive layer, where the etching compound used in the first etching process is relatively selective to the conductive layer's materials. Embodiments also include performing a second, contact related etching process that removes a portion of any misaligned contacts that were exposed by the first etching process, where the etching compound used in the second etching process is selective to the contacts' materials. The embodiments can be used to form vias and other interconnect structures as well. The modified contacts and vias are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.