Patents by Inventor J. Ireland

J. Ireland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130034119
    Abstract: A via chain testing structure includes: a substrate; a dielectric layer disposed on the substrate; a first via chain disposed on dielectric layer; a second via chain, being disposed on the dielectric on both sides of the first via chain and in thermal proximity with the first via chain; a first heating source disposed under the substrate, for providing thermal heat to the first via chain; and an electrical current source for heating the second via chain so the second via chain acts as a second heating source for the first via chain.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Inventors: Philip J. Ireland, Wen-Sung Chiang
  • Publication number: 20130030390
    Abstract: Needle comprising a polyarylene material comprising a polyarylene. The needle can meet all the advantages of metal, while avoiding its drawbacks. It has a high rigidity and ductility, and is excellent in penetrability and ability to hold a sharp edge. It is easily disposable and recyclable. It is non toxic and non irritant.
    Type: Application
    Filed: March 16, 2011
    Publication date: January 31, 2013
    Applicant: SOLVAY SPECIALTY POLYMERS USA, LLC
    Inventors: Jean-Baptiste Bonnadier, Daniel J. Ireland, Henri Massillon
  • Publication number: 20130026647
    Abstract: A via structure includes at least a first via set and a second via set electrically connected to the first via set. There is at least one via in the first via set and at least one via in the second via set. The via in the first via set has a cross-sectional area which is larger than that of the via in the second via set.
    Type: Application
    Filed: July 31, 2011
    Publication date: January 31, 2013
    Inventor: Philip J. Ireland
  • Publication number: 20120326283
    Abstract: Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous.
    Type: Application
    Filed: September 7, 2012
    Publication date: December 27, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kyle K. Kirby, Philip J. Ireland
  • Publication number: 20120306084
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 6, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Alan G. Wood, Philip J. Ireland
  • Publication number: 20120272069
    Abstract: A method and apparatus is shown to allow the creation of sound programmers and complementary sound decoders that may be securely downloaded with sound and IPL data and that will operate in power limited environments with resistance to power drop outs and are significant improvements beyond prior art devices.
    Type: Application
    Filed: May 24, 2012
    Publication date: October 25, 2012
    Inventor: A. J. Ireland
  • Publication number: 20120267786
    Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.
    Type: Application
    Filed: April 22, 2011
    Publication date: October 25, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Philip J. Ireland, Sarah A. Niroumand
  • Patent number: 8283785
    Abstract: Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: October 9, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Philip J. Ireland
  • Publication number: 20120068348
    Abstract: Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous.
    Type: Application
    Filed: September 20, 2010
    Publication date: March 22, 2012
    Inventors: Kyle K. Kirby, Philip J. Ireland
  • Publication number: 20110293757
    Abstract: Compositions for the treatment and/or prevention of cancer are described. Preferably the composition comprises a therapeutically effective amount of tea tree oil from Melaleuca alternifolia, together with a pharmaceutically or therapeutically acceptable carrier and/or diluent. Methods for the treatment and/or prevention of cancer are also described. Preferably the method is used for the treatment and prevention of skin cancer. More preferably, the method is used for the treatment and prevention of basal cell carcinoma, squamous cell carcinoma and/or melanoma.
    Type: Application
    Filed: July 17, 2009
    Publication date: December 1, 2011
    Applicant: Novasel Australia Pty. Ltd.
    Inventors: Thomas V. Riley, Sara J. Greay, Christine F. Carson, Manfred W. Beilharz, Demelza J. Ireland, Haydn T. Kissick
  • Publication number: 20110278738
    Abstract: This document discusses, among other things, example systems including integrated circuit contacts configured to reduce the likelihood of shorting to unrelated portions of overlying conductive material due to contact misalignment.
    Type: Application
    Filed: July 28, 2011
    Publication date: November 17, 2011
    Inventor: Philip J. Ireland
  • Publication number: 20110254163
    Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.
    Type: Application
    Filed: June 28, 2011
    Publication date: October 20, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Philip J. Ireland, Howard E. Rhodes
  • Publication number: 20110212618
    Abstract: Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in reduced interconnect resistance, I2R losses, and defects or variations due to cusping. Embodiments of the methods involve forming an opening in an insulating layer, where the opening forms a trench that exposes an underlying portion of a metal layer. Additional embodiments involve depositing multiple layers of conductive material within the opening and above the insulating layer, where one of the conductive layers includes aluminum and is deposited using a “cold aluminum” process, and a second one of the conductive layers also includes aluminum, but is deposited using a “hot aluminum” process. The interconnect structures are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
    Type: Application
    Filed: May 16, 2011
    Publication date: September 1, 2011
    Inventor: Philip J. Ireland
  • Patent number: 7989957
    Abstract: Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer due to contact misalignment. Embodiments for forming the integrated circuit include performing a first etching process to pattern the conductive layer, where the etching compound used in the first etching process is relatively selective to the conductive layer's materials. Embodiments also include performing a second, contact related etching process that removes a portion of any misaligned contacts that were exposed by the first etching process, where the etching compound used in the second etching process is selective to the contacts' materials. The embodiments can be used to form vias and other interconnect structures as well. The modified contacts and vias are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Philip J. Ireland
  • Patent number: 7968403
    Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: June 28, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Philip J. Ireland, Howard E. Rhodes
  • Patent number: 7943503
    Abstract: Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in reduced interconnect resistance, I2R losses, and defects or variations due to cusping. Embodiments of the methods involve forming an opening in an insulating layer, where the opening forms a trench that exposes an underlying portion of a metal layer. Additional embodiments involve depositing multiple layers of conductive material within the opening and above the insulating layer, where one of the conductive layers includes aluminum and is deposited using a “cold aluminum” process, and a second one of the conductive layers also includes aluminum, but is deposited using a “hot aluminum” process. The interconnect structures are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Philip J. Ireland
  • Publication number: 20100268192
    Abstract: Medical tubing (T), such as a guidewire, a stent, a catheter or a hollow needle, made of a kinked rigid-rod polyarylene exhibiting a outstanding characteristics including high torqueability, high pushability and high flexibility and which can be easily thin-wall extruded under especially harsh conditions.
    Type: Application
    Filed: April 21, 2010
    Publication date: October 21, 2010
    Applicant: SOLVAY ADVANCED POLYMERS, L.L.C.
    Inventors: Mohammad Jamal EL-HIBRI, Brian BALENO, Nikica MALJKOVIC, Bianca Sadicoff SHEMPER, Jean-Baptiste BONNADIER, Daniel J. IRELAND, Henri N. J. MASSILLON
  • Patent number: 7726612
    Abstract: A method and apparatus is shown to allow an integrated expanded control capability of digital locomotives on model railroad layouts that also permit compatible speed and direction operation simultaneously for non-digital or conventional locomotives alongside. The improvements employ mixed-mode control encoding and decoding algorithms and methods that are expanded beyond the prior art for control mode changes used on model railroad layouts.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: June 1, 2010
    Inventor: Anthony J. Ireland
  • Publication number: 20100096672
    Abstract: Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer due to contact misalignment. Embodiments for forming the integrated circuit include performing a first etching process to pattern the conductive layer, where the etching compound used in the first etching process is relatively selective to the conductive layer's materials. Embodiments also include performing a second, contact related etching process that removes a portion of any misaligned contacts that were exposed by the first etching process, where the etching compound used in the second etching process is selective to the contacts' materials. The embodiments can be used to form vias and other interconnect structures as well. The modified contacts and vias are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
    Type: Application
    Filed: December 28, 2009
    Publication date: April 22, 2010
    Inventor: Philip J. Ireland
  • Publication number: 20100059966
    Abstract: The present disclosure provides a system for loading and unloading a watercraft from a trailer that enables the process to be accomplished without the need to stand on the submerged ground surface. In some embodiments the trailer includes an adjustable platform that provides an area upon which the operator can stand while loading and unloading the watercraft from the trailer. The present disclosure also provides a method of loading and unloading a boat that includes the step of pushing or pulling the boat while standing on a platform that extends from the trailer.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 11, 2010
    Inventor: Ralph J. Ireland