Abstract: A method of fabricating a semiconductor device. The method produces a device that includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.

Abstract: This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal which is in contact with the substrate, and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.

Abstract: A reticle for manufacturing a semiconductor device. The reticle includes cutouts that permit material deposited through the reticle and onto a surface of a semiconductor device being manufactured to form the shape of the cutouts. Shapes defined in the cutouts and produced on the semiconductor device include first and second topographic structures, where the first are made up of conductive lead lines, and the second made up of fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the first topographic structures. The first and second topographic structures can be arranged in a generally repeating array on the substrate.

Abstract: Disclosed is a circuit element that includes a thermoplastic substrate and a conductive trace at least partially embedded in the thermoplastic substrate. Also disclosed is a method of forming a circuit element. The method includes the steps of providing a thermoplastic substrate having a softening temperature, printing a conductive ink onto the thermoplastic substrate to form a trace, and embedding the trace into the thermoplastic substrate by heating the thermoplastic substrate to a temperature above about the softening temperature about the trace.

Abstract: An exemplary implementation of the invention is a process for forming passivation protection on a semiconductor assembly by the steps of: forming a layer of oxide over patterned metal lines having sidewalls; forming a first passivation layer of silicon nitride over the layer of oxide such that the first passivation layer of silicon nitride resides along the sidewalls of metal lines and pinches off a gap between the metal lines; performing a facet etch to remove material from the edges of the first passivation layer of silicon nitride and re-deposits some of removed material across a pinch-off junction; forming a second passivation layer of silicon nitride on the first passivation layer of silicon nitride.

Abstract: A fill pattern for a semiconductor device. The device includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.

Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. At least two opposing contoured, merging dielectric surfaces define at least one elongated passageway which has at least one. A conductive material then substantially fills the at least one opening and at least one elongated passageway to form at least one electrical interconnect guided by the at least one elongated passageway and extended through the layer of dielectric material along the length to electrically connect at least two of the components of the integrated circuit.

Abstract: The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.

Abstract: A metal line layout which includes two separate control spaces to address capacitive issues along speed sensitive pathways in an integrated circuit structure without negatively impacting Werner Fill processing. One control space (i.e., DRCgap1) is for decreasing the spacing between various metal features to standardize such spacing, and a second control space (i.e., DRCgap2) is for addressing capacitance issues along speed sensitive pathways. Between speed sensitive pathways, spacing of added metal features provided to long parallel metal lines are maintained at the second control spacing DRCgap2. Spaces at the ends of such long parallel metal lines are reduced to the first control spacing DRCgap1 in order to best fill three-way-intersections (TWIs) with subsequent depositions.

Abstract: Embodiments of the invention concern modifying the layout of one or more metal layers of an integrated circuit before patterning those layers, so that an intermetal dielectric layer (IDL) subsequently deposited over the top surface of the patterned layer will be substantially self-planarized. The spacing between parallel edges of adjacent first metal lines and features is standardized, and one or more additional metal features are included in areas where an intersection exists. The additional metal features serve to maintain the elevation of the top surface of the IDL at the same height across the intersections, thus achieving self-planarization across the entire top surface of the IDL, without the need for a thicker than desired IDL. The modified metal layers are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.

Abstract: A method for generating a depth-indexed data structure for a reaming operation includes receiving, by a software process, i) well logging data that includes time-indexed data and depth measurement data for an oil well drilling rig, ii) a selection identifying a depth range for a reaming operation by the drilling rig, and iii) values for a certain parameter indicating an operating mode for the drilling rig. Then the software process extracts, responsive to the selected depth range and one of the values of the parameter, a section from the well logging data within the selected depth range, and generates from the section the depth-indexed data structure for the reaming operation.

Abstract: Embodiments concern contacts for use in integrated circuits, and methods of their manufacture, which result in a reduced likelihood of shorting between unrelated portions of an overlying conductive layer across misaligned contacts. Embodiments of the method involve performing a first etching process to pattern the conductive layer, where the etching compound used in the first etching process is relatively selective to the conductive layer's materials. Embodiments of the method also involve performing a second, contact related etching process that removes a portion of any misaligned contacts that were exposed by the first etching process, where the etching compound used in the second etching process is selective to the contacts' materials. The embodiments of the method could be used to form vias and other interconnect structures as well.

Abstract: A fill pattern for a semiconductor device such as a memory cell. The memory cell includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.

Abstract: Titanium-containing films exhibiting excellent uniformity and step coverage are deposited on semiconductor wafers in a cold wall reactor which has been modified to discharge plasma into the reaction chamber. Titanium tetrabromide, titanium tetraiodide, or titanium tetrachloride, along with hydrogen, enter the reaction chamber and come in contact with a heated semiconductor wafer, thereby depositing a thin titanium-containing film on the wafer's surface. Step coverage and deposition rate are enhanced by the presence of the plasma. The use of titanium tetrabromide or titanium tetraiodide instead of titanium tetrachloride also increases the deposition rate and allows for a lower reaction temperature. Titanium silicide and titanium nitride can also be deposited by this method by varying the gas incorporated with the titanium precursors.

Abstract: A reticle for manufacturing a semiconductor device. The reticle includes cutouts that permit material deposited through the reticle and onto a surface of a semiconductor device being manufactured to form the shape of the cutouts. Shapes defined in the cutouts and produced on the semiconductor device include first and second topographic structures, where the first are made up of conductive lead lines, and the second made up of fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the first topographic structures. The first and second topographic structures can be arranged in a generally repeating array on the substrate.

Abstract: A method of fabricating a semiconductor device. The method produces a device that includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.

Abstract: A fill pattern for a semiconductor device. The device includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.

Abstract: A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.

Abstract: The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.