Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

Abstract: A system and method for interference detection. The system and method receives flight data comprising a plurality of flights. The system and method identifies a plurality of signal drop events based on at least the flight data. The system and method determines one or more co-located signal drop event subsets based on at least the plurality of signal drop events and filter criteria. The system and method determines one or more interference events based on the one or more co-located signal drop event subsets, wherein each of the one or more co-located signal drop event subsets is based on at least two or more of the plurality of signal drop events.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a thermal plug and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure over the semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a thermal plug extending from a top side of the semiconductor substrate into an active region of the semiconductor substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; a first field plate on a first side of the gate structure; and a second field plate on a second side of the gate structure, independent from the first field plate.

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer.

Abstract: A system and method for detection of GNSS signal spoofing with high integrity error bounding determines a parity space formulation for coordinates of a GNSS-driven master position solution (e.g., fully absolute/GNSS or blended GNSS/IRS solution) and a corresponding coasted position solution (e.g., less frequently GNSS-updated), wherein a parity vector expresses consistency of the master coordinate with the coasted coordinate. Based on a desired level of missed detection, protection levels are determined for the parity space formulation, and integrity bounds on the master and coasted solutions calculated. The parity vector is compared with a detection threshold. If, for any solution component (e.g., direction, axis) of the master solution, the parity vector meets or exceeds the threshold, a spoofer is detected and a coasted solution is propagated with its coasted integrity bound. If no spoofer is detected, the master solution and its master integrity bound are propagated as output.

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

Abstract: A local area detection and alerting system (LDAS) for detecting potential GNSS spoofing within a protected airspace includes a ground-based control station and several RF interference (RFI) control stations spaced to define the protected airspace. Each RFI control station includes two or more reference GNSS signal receivers in communication with two or more reception (Rx) antennas, each antenna having a surveyed true location and distinct height. The reference receivers continually determine GNSS-derived absolute positions of each antenna, which are compared to their true locations to determine if GNSS spoofing is responsible for measurement anomalies. Any detection of potential spoofing is forwarded to the control station, which broadcasts regular LDAS updates indicating the presence or absence of potential spoofing to all aircraft operating within a transmission range surrounding the protected airspace.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.

Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.

Abstract: A light modulated electron source utilizes a photon-beam source to modulate the emission current of an electron beam emitted from a silicon-based field emitter. The field emitter's cathode includes a protrusion fabricated on a silicon substrate and having an emission tip covered by a coating layer. An extractor generates an electric field that attracts free electrons toward the emission tip for emission as part of the electron beam. The photon-beam source generates a photon beam including photons having an energy greater than the bandgap of silicon, and includes optics that direct the photon beam onto the emission tip, whereby each absorbed photon creates a photo-electron that combines with the free electrons to enhance the electron beam's emission current. A controller modulates the emission current by controlling the intensity of the photon beam applied to the emission tip. A monitor measures the electron beam and provides feedback to the controller.

Abstract: A system and method for interference detection. The system and method receives flight data comprising a plurality of flights. The system and method identifies a plurality of signal drop events based on at least the flight data. The system and method determines one or more co-located signal drop event subsets based on at least the plurality of signal drop events and filter criteria. The system and method determines one or more interference events based on the one or more co-located signal drop event subsets, wherein each of the one or more co-located signal drop event subsets is based on at least two or more of the plurality of signal drop events.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.

Abstract: Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to lateral bipolar transistors and methods of manufacture. The structure includes: an extrinsic base comprising semiconductor material; an intrinsic base comprising semiconductor material which is located below the extrinsic base; a polysilicon emitter on a first side of the extrinsic base; a raised collector on a second side of the extrinsic base; and sidewall spacers on the extrinsic base which separate the extrinsic base from the polysilicon emitter and the raised collector.