Patents by Inventor J. Joseph

J. Joseph has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11637181
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to lateral bipolar transistors and methods of manufacture. The structure includes: an extrinsic base comprising semiconductor material; an intrinsic base comprising semiconductor material which is located below the extrinsic base; a polysilicon emitter on a first side of the extrinsic base; a raised collector on a second side of the extrinsic base; and sidewall spacers on the extrinsic base which separate the extrinsic base from the polysilicon emitter and the raised collector.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 25, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Alvin J. Joseph, Alexander Derrickson, Judson R. Holt, John J. Pekarik
  • Patent number: 11605649
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: March 14, 2023
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Mark D. Levy, Siva P. Adusumilli, Alvin J. Joseph, Ramsey Hazbun
  • Publication number: 20230064512
    Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.
    Type: Application
    Filed: November 24, 2021
    Publication date: March 2, 2023
    Inventors: Vibhor Jain, John J. Pekarik, Alvin J. Joseph, Alexander M. Derrickson, Judson R. Holt
  • Publication number: 20230065785
    Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.
    Type: Application
    Filed: December 20, 2021
    Publication date: March 2, 2023
    Applicant: GlobalFoundries U.S. Inc.
    Inventors: Jagar Singh, Alexander M. Derrickson, Alvin J. Joseph, Andreas Knorr, Judson R. Holt
  • Publication number: 20230057695
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to lateral bipolar transistors and methods of manufacture. The structure includes: an extrinsic base comprising semiconductor material; an intrinsic base comprising semiconductor material which is located below the extrinsic base; a polysilicon emitter on a first side of the extrinsic base; a raised collector on a second side of the extrinsic base; and sidewall spacers on the extrinsic base which separate the extrinsic base from the polysilicon emitter and the raised collector.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 23, 2023
    Inventors: Vibhor Jain, Alvin J. Joseph, Alexander Derrickson, Judson R. Holt, John J. Pekarik
  • Publication number: 20230034728
    Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Applicant: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Zhong-Xiang He, Richard J. Rassel, Alvin J. Joseph, Ramsey M. Hazbun, Jeonghyun Hwang, Mark D. Levy
  • Publication number: 20220406833
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 22, 2022
    Inventors: Siva P. ADUSUMILLI, Vibhor JAIN, Alvin J. JOSEPH, Steven M. SHANK
  • Patent number: 11515158
    Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 29, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Ramsey Hazbun, Alvin J. Joseph, Siva P. Adusumilli, Cameron Luce
  • Publication number: 20220352210
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.
    Type: Application
    Filed: May 3, 2021
    Publication date: November 3, 2022
    Inventors: Mark D. LEVY, Siva P. ADUSUMILLI, Alvin J. JOSEPH, Ramsey HAZBUN
  • Publication number: 20220336180
    Abstract: A light modulated electron source utilizes a photon-beam source to modulate the emission current of an electron beam emitted from a silicon-based field emitter. The field emitter's cathode includes a protrusion fabricated on a silicon substrate and having an emission tip covered by a coating layer. An extractor generates an electric field that attracts free electrons toward the emission tip for emission as part of the electron beam. The photon-beam source generates a photon beam including photons having an energy greater than the bandgap of silicon, and includes optics that direct the photon beam onto the emission tip, whereby each absorbed photon creates a photo-electron that combines with the free electrons to enhance the electron beam's emission current. A controller modulates the emission current by controlling the intensity of the photon beam applied to the emission tip. A monitor measures the electron beam and provides feedback to the controller.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 20, 2022
    Inventors: Edgardo Garcia Berrios, J. Joseph Armstrong, Yinying Xiao-Li, John Fielden, Yung-Ho Alex Chuang
  • Patent number: 11476289
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 18, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, Vibhor Jain, Alvin J. Joseph, Steven M. Shank
  • Patent number: 11417492
    Abstract: A light modulated electron source utilizes a photon-beam source to modulate the emission current of an electron beam emitted from a silicon-based field emitter. The field emitter's cathode includes a protrusion fabricated on a silicon substrate and having an emission tip covered by a coating layer. An extractor generates an electric field that attracts free electrons toward the emission tip for emission as part of the electron beam. The photon-beam source generates a photon beam including photons having an energy greater than the bandgap of silicon, and includes optics that direct the photon beam onto the emission tip, whereby each absorbed photon creates a photo-electron that combines with the free electrons to enhance the electron beam's emission current. A controller modulates the emission current by controlling the intensity of the photon beam applied to the emission tip. A monitor measures the electron beam and provides feedback to the controller.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 16, 2022
    Assignee: KLA Corporation
    Inventors: Edgardo Garcia Berrios, J. Joseph Armstrong, Yinying Xiao-Li, John Fielden, Yung-Ho Alex Chuang
  • Patent number: 11387353
    Abstract: A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 12, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Jagar Singh, Sudarshan Narayanan, Alvin J. Joseph, William J. Taylor, Jr., Jeffrey B. Johnson
  • Publication number: 20220189821
    Abstract: A structure includes an active device over an area of a substrate, and a heat spreading isolation structure adjacent the active device. The isolation structure includes a dielectric layer above a heat-conducting layer. The heat-conducting layer may include polycrystalline graphite. The heat-conducting layer provides a heat sink, which provides a high thermal conductivity path for heat with low electrical conductivity. The heat-conducting layer may extend into the substrate. The substrate may include an SOI substrate in which case the heat-conducting layer may extend through the buried insulator thereof.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 16, 2022
    Inventors: Mark D. Levy, Siva P. Adusumilli, Alvin J. Joseph
  • Publication number: 20220181317
    Abstract: Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Inventors: Anthony K. Stamper, Michel J. Abou-Khalil, John J. Ellis-Monaghan, Randy Wolf, Alvin J. Joseph, Aaron Vallett
  • Patent number: 11355409
    Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: June 7, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Hanyi Ding, Vibhor Jain, Alvin J. Joseph, Anthony K. Stamper
  • Patent number: 11284365
    Abstract: A system for time synchronization over redundant switch-based avionics networks is disclosed. The system includes a master or source clock for determining precise UTC timing information from received satellite signals and generating time marks based on the timing information. The source clock generates network-compatible timing messages and forwards the timing messages to network switches within the switch-based avionics networks. The network switches modify the timing information to account for switch-based delays and forward the modified timing messages to destination clocks in aircraft end systems. The end systems relay timing messages back to the source clock via the network switches, the timing information again modified by the network switches according to switch-based delays, and based on the precise timing information exchanged destination clocks in end systems throughout the switched network can precisely synchronize to the source clock.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 22, 2022
    Assignee: Rockwell Collins, Inc.
    Inventors: Daniel J. Kaplan, Yeshani D. WijesekaraGamachchige, Andrea P. Gonzalez, Christopher A. Hohensee, Angelo J. Joseph, Nels Waineo, Christopher Kistler, Jason R. Owen
  • Patent number: 11264457
    Abstract: Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: March 1, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Mark Levy, Siva P. Adusumilli, Steven M. Shank, Alvin J. Joseph, Anthony K. Stamper
  • Publication number: 20210399116
    Abstract: A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 23, 2021
    Inventors: Jagar Singh, Sudarshan Narayanan, Alvin J. Joseph, William J. Taylor, JR., Jeffrey B. Johnson
  • Patent number: 11195715
    Abstract: Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: December 7, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, Cameron Luce, Ramsey Hazbun, Mark Levy, Anthony K. Stamper, Alvin J. Joseph