Patents by Inventor Jack Kavalieros

Jack Kavalieros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
    Patent number: 8110877
    Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Gilbert Dewey, Matthew V. Metz, Jack Kavalieros, Robert S. Chau
  • Method of forming self-aligned low resistance contact layer
    Patent number: 8088665
    Abstract: Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor and a second precursor to selectively deposit an amorphous semiconductor layer onto each of the source and drain regions. A metal layer is then deposited over the amorphous semiconductor layer on each of the source and drain regions. An annealing process is then performed on the substrate to allow the metal layer to react with amorphous semiconductor layer to form a low resistance contact layer on each of the source and drain regions. The low resistance contact layer on each of the source and drain regions can be formed as either a silicide layer or germanide layer depending on the type of precursors used.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: January 3, 2012
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Jason W. Klaus, Ravi Pillarisetty, Niloy Mukherjee, Jack Kavalieros, Sean King
  • TUNNEL FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING SAME
    Publication number: 20110315960
    Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.
    Type: Application
    Filed: September 2, 2011
    Publication date: December 29, 2011
    Inventors: Niti Goel, Wilman Tsai, Jack Kavalieros
  • MULTIPLE-GATE TRANSISTORS AND PROCESSES OF MAKING SAME
    Publication number: 20110312140
    Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.
    Type: Application
    Filed: August 24, 2011
    Publication date: December 22, 2011
    Inventors: Ravi Pillarisetty, Jack Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung
  • Semiconductor device structures and methods of forming semiconductor structures
    Patent number: 8071983
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: December 6, 2011
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau, Brian S. Doyle
  • Multiple-gate transistors and processes of making same
    Patent number: 8063447
    Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: November 22, 2011
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Jack Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung
  • Tunnel field effect transistor and method of manufacturing same
    Patent number: 8026509
    Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: September 27, 2011
    Assignee: Intel Corporation
    Inventors: Niti Goel, Wilman Tsai, Jack Kavalieros
  • Methods for fabricating PMOS metal gate structures
    Patent number: 8021940
    Abstract: Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: September 20, 2011
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Mark L. Doczy, Gilbert Dewey, Jack Kavalieros
  • Isolated tri-gate transistor fabricated on bulk substrate
    Patent number: 7973389
    Abstract: A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: July 5, 2011
    Assignee: Intel Corporation
    Inventors: Rafael Rios, Jack Kavalieros, Stephen M. Cea
  • Multi-gate III-V quantum well structures
    Publication number: 20110156004
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Marko Radosavljevic, Uday Shah, Gilbert Dewey, Niloy Mukherjee, Robert S. Chau, Jack Kavalieros, Ravi Pillarisetty, Titash Rakshit, Matthew V. Metz
  • BUFFER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION
    Publication number: 20110156098
    Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 30, 2011
    Inventors: Prashant Majhi, Jack Kavalieros, Wilman Tsai
  • FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR
    Publication number: 20110156145
    Abstract: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
    Type: Application
    Filed: March 8, 2011
    Publication date: June 30, 2011
    Inventors: Marko Radosavljevic, Amlan Majumdar, Suman Datta, Jack Kavalieros, Brian S. Doyle, Justin K. Brask, Robert S. Chau
  • Sandwiched metal structure silicidation for enhanced contact
    Patent number: 7968457
    Abstract: Embodiments of an apparatus and methods for forming enhanced contacts using sandwiched metal structures are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: June 28, 2011
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Jack Kavalieros, Robert S. Chau
  • APPARATUS AND METHODS FOR FORMING A MODULATION DOPED NON-PLANAR TRANSISTOR
    Publication number: 20110140171
    Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: February 23, 2011
    Publication date: June 16, 2011
    Inventors: Ravi Pillarisetty, Mantu Hudait, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Jack Kavalieros
  • Forming abrupt source drain metal gate transistors
    Patent number: 7951673
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20110121393
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: February 4, 2011
    Publication date: May 26, 2011
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Inducing Strain in the Channels of Metal Gate Transistors
    Publication number: 20110115028
    Abstract: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.
    Type: Application
    Filed: January 26, 2011
    Publication date: May 19, 2011
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Brian S. Doyle
  • Metalgate electrode for PMOS transistor
    Patent number: 7936025
    Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: May 3, 2011
    Assignee: Intel Corporation
    Inventors: Robert Chau, Mark Doczy, Brian Doyle, Jack Kavalieros
  • Buffer structure for semiconductor device and methods of fabrication
    Patent number: 7928468
    Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: April 19, 2011
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Jack Kavalieros, Wilman Tsai
  • Fabrication of channel wraparound gate structure for field-effect transistor
    Patent number: 7915167
    Abstract: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Amlan Majumdar, Suman Datta, Jack Kavalieros, Brian S. Doyle, Justin K. Brask, Robert S. Chau