Patents by Inventor Jack Kavalieros

Jack Kavalieros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and methods for forming a modulation doped non-planar transistor
    Patent number: 7915642
    Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Mantu Hudait, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Jack Kavalieros
  • Inducing strain in the channels of metal gate transistors
    Patent number: 7902058
    Abstract: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Brian S. Doyle
  • Block contact architectures for nanoscale channel transistors
    Patent number: 7898041
    Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: March 1, 2011
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Jack Kavalieros, Mark L. Doczy, Justin K. Brask, Uday Shah, Suman Datta, Robert S. Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 7893506
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • CMOS device with metal and silicide gate electrodes and a method for making it
    Patent number: 7883951
    Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Field effect transistor with metal source/drain regions
    Patent number: 7879675
    Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: February 1, 2011
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Suman Datta, Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Amian Majumdar, Robert S. Chau
  • APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMANCE
    Publication number: 20110018063
    Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: October 1, 2010
    Publication date: January 27, 2011
    Inventors: Brian Doyle, Titash Rakshit, Jack Kavalieros
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Patent number: 7875937
    Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: January 25, 2011
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Suman Datta, Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Robert S. Chau
  • Germanium on insulator using compound semiconductor barrier layers
    Publication number: 20100327317
    Abstract: Embodiments of an apparatus and methods for providing germanium on insulator using a large bandgap barrier layer are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventors: Ravi Pillarisetty, Mantu Hudait, Marko Radosavljevic, Benjamin Chu-Kung, Jack Kavalieros
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20100295129
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: August 4, 2010
    Publication date: November 25, 2010
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Replacement spacers for MOSFET fringe capacitance reduction and processes of making same
    Patent number: 7838373
    Abstract: A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: November 23, 2010
    Assignee: Intel Corporation
    Inventors: Martin Giles, Titash Rakshit, Lucian Shifren, Jack Kavalieros, Willy Rachmady
  • Notched-base spacer profile for non-planar transistors
    Patent number: 7833887
    Abstract: A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Jack Kavalieros
  • Apparatus and methods for improving multi-gate device performance
    Patent number: 7833889
    Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance including methods to fabricate a plurality of multi-gate fins from a diffused body of a substantially planar structure that is substantially electrically isolated using a shallow trench region are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Brian Doyle, Titash Rakshit, Jack Kavalieros
  • METHODS OF FORMING NANODOTS USING SPACER PATTERNING TECHNIQUES AND STRUCTURES FORMED THEREBY
    Publication number: 20100285279
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots.
    Type: Application
    Filed: December 31, 2007
    Publication date: November 11, 2010
    Inventors: Brian Doyle, Been-Yih Jin, Jack Kavalieros, Robert Chau
  • Unity beta ratio tri-gate transistor static random access memory (SRAM)
    Patent number: 7825437
    Abstract: In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 7825481
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Spacer patterned augmentation of tri-gate transistor gate length
    Patent number: 7820512
    Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: October 26, 2010
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • FORMING INTEGRATED CIRCUITS WITH REPLACEMENT METAL GATE ELECTRODES
    Publication number: 20100219456
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Application
    Filed: May 17, 2010
    Publication date: September 2, 2010
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Patent number: 7785958
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Uday Shah, Matthew V. Metz, Suman Datta, Ramune Nagisetty, Robert S. Chau
  • Self-aligned tunneling pocket in field-effect transistors and processes to form same
    Patent number: 7777282
    Abstract: A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: August 17, 2010
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Wilman Tsai, Jack Kavalieros, Ravi Pillarisetty, Benjamin Chu-Kung