Patents by Inventor Jack Kavalieros

Jack Kavalieros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Forming high-k dielectric layers on smooth substrates
    Patent number: 7615441
    Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 10, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Gilbert Dewey, Robert S. Chau
  • Complementary Metal Oxide Semiconductor Integrated Circuit Using Raised Source Drain and Replacement Metal Gate
    Publication number: 20090261391
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Inventors: Jack KAVALIEROS, Annalisa CAPPELLANI, Justin K. BRASK, Mark L. DOCZY, Matthew V. METZ, Suman DATTA, Chris E. BARNS, Robert S. CHAU
  • Angled implantation for removal of thin film layers
    Patent number: 7595248
    Abstract: Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: September 29, 2009
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Justin K. Brask, Justin S. Sandford, Jack Kavalieros, Matthew V. Metz
  • APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMACE
    Publication number: 20090230478
    Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 17, 2009
    Inventors: Ravi Pillarisetty, Brian Doyle, Titash Rakshit, Jack Kavalieros
  • SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES
    Publication number: 20090218603
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Application
    Filed: May 8, 2009
    Publication date: September 3, 2009
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau, Brian S. Doyle
  • Removing a high-k gate dielectric
    Patent number: 7575991
    Abstract: A metal oxide layer on a substrate is converted at least partly to a metal layer. At least part of the metal layer is covered by an oxidation resistant cover. The covered layer and underlying metal may be removed, for example, using acid.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 18, 2009
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Robert L. Norman, Justin K. Brask, Jack Kavalieros, Matthew Metz, Suman Datta, Robert S. Chau
  • Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
    Patent number: 7569443
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: August 4, 2009
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Annalisa Cappellani, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Chris E. Barns, Robert S. Chau
  • METAL GATE DEVICE WITH REDUCED OXIDATION OF A HIGH-K GATE DIELECTRIC
    Publication number: 20090179282
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.
    Type: Application
    Filed: January 14, 2009
    Publication date: July 16, 2009
    Inventors: Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Matthew V. Mertz, Mark L. Doczy, Suman Datta, Robert S. Chau
  • Tri-gate devices and methods of fabrication
    Patent number: 7560756
    Abstract: The present invention is a semiconductor device comprising a carbon nanotube body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the carbon nanotube body and on the laterally opposite sidewalls of the carbon nanotube body. A gate electrode is formed on the gate dielectric on the top surface of the carbon nanotube body and adjacent to the gate dielectric on the laterally opposite sidewalls of the carbon nanotube body.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Brian S. Doyle, Jack Kavalieros, Douglas Barlage, Suman Datta
  • METHODS FOR FABRICATING PMOS METAL GATE STRUCTURES
    Publication number: 20090166769
    Abstract: Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: INTEL CORPORATION
    Inventors: Matthew V. Metz, Mark L. Doczy, Gilbert Dewey, Jack Kavalieros
  • Spacer patterned augmentation of tri-gate transistor gate length
    Publication number: 20090168498
    Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • Unity beta ratio tri-gate transistor static radom access memory (SRAM)
    Publication number: 20090166680
    Abstract: In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • Reducing Ambipolar Conduction in Carbon Nanotube Transistors
    Publication number: 20090159872
    Abstract: Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.
    Type: Application
    Filed: January 26, 2009
    Publication date: June 25, 2009
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Marko Radosavljevic, Amlan Majumdar, Justin K. Brask, Robert S. Chau
  • Methods for patterning a semiconductor film
    Patent number: 7547637
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: June 16, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau, Brian S. Doyle
  • METHOD OF FORMING A NONPLANAR TRANSISTOR WITH SIDEWALL SPACERS
    Publication number: 20090149012
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Application
    Filed: February 11, 2009
    Publication date: June 11, 2009
    Inventors: Justin K. Brask, Brian S. Doyle, Jack Kavalieros, Mark Doczy, Uday Shah, Robert S. Chau
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20090142897
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 4, 2009
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material
    Patent number: 7531437
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Brian S. Doyle, Jack Kavalieros, Mark Doczy, Uday Shah, Robert S. Chau
  • Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer
    Patent number: 7531404
    Abstract: A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 ? to 60 ?. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Sangwoo Pae, Jose Maiz, Justin Brask, Gilbert Dewey, Jack Kavalieros, Robert Chau, Suman Datta
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 7518196
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Tri-gate devices and methods of fabrication
    Patent number: 7514346
    Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Brian S. Doyle, Jack Kavalieros, Douglas Barlage, Suman Datta, Scott A. Hareland