Patents by Inventor Jack Kavalieros

Jack Kavalieros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BUFFER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION
    Publication number: 20100163848
    Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Prashant Majhi, Jack Kavalieros, Wilman Tsai
  • Tunnel field effect transistor and method of manufacturing same
    Publication number: 20100163845
    Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventors: Niti Goel, Wilman Tsai, Jack Kavalieros
  • Apparatus and methods for forming a modulation doped non-planar transistor
    Publication number: 20100163927
    Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventors: Ravi Pillarisetty, Mantu Hudait, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Jack Kavalieros
  • Methods of forming low interface resistance rare earth metal contacts and structures formed thereby
    Publication number: 20100155954
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 24, 2010
    Inventors: Niloy Mukherjee, Matt Metz, Gilbert Dewey, Jack Kavalieros, Robert S. Chau
  • Metal-insulator-semiconductor tunneling contacts
    Publication number: 20100155846
    Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 24, 2010
    Inventors: Niloy Mukherjee, Gilbert Dewey, Matthew V. Metz, Jack Kavalieros, Robert S. Chau
  • FORMING ABRUPT SOURCE DRAIN METAL GATE TRANSISTORS
    Publication number: 20100151669
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 17, 2010
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Lateral undercut of metal gate in SOI device
    Patent number: 7736956
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Suman Datta, Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Gilbert Dewey, Mark L. Doczy, Robert S. Chau
  • Forming integrated circuits with replacement metal gate electrodes
    Patent number: 7718479
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Patent number: 7709909
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin K. Brask, Jack Kavalieros, Matthew V. Metz, Adrian B. Sherrill, Markus Kuhn, Robert S. Chau
  • Methods for inducing strain in non-planar transistor structures
    Patent number: 7709312
    Abstract: Methods for inducing compressive strain in channel region of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include forming trenches in a semiconductor body adjacent to gate structure spacers. The semiconductor body can be situated on a substrate and in a different plane relative to the substrate. The gate structure can be situated on the semiconductor body and the silicon fin and perpendicular to the semiconductor body. After formation of the semiconductor body and the gate structure on the substrate, a dielectric material can be conformally deposited on the substrate and etched to form spacers on the semiconductor body and the gate structure. The substrate can be patterned and etched to form trenches in the semiconductor body adjacent to the spacers on the gate structure. A strain material can be introduced into the trenches.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Brian Doyle, Uday Shah, Jack Kavalieros
  • Method of forming abrupt source drain metal gate transistors
    Patent number: 7704833
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Isolated tri-gate transistor fabricated on bulk substrate
    Publication number: 20100059821
    Abstract: A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.
    Type: Application
    Filed: November 10, 2009
    Publication date: March 11, 2010
    Inventors: Rafael Rios, Jack Kavalieros, Stephen M. Cea
  • Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode
    Patent number: 7671471
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Uday Shah, Chris E. Barns, Matthew V. Metz, Suman Datta, Annalisa Cappellani, Robert S. Chau
  • Self-aligned tunneling pocket in field-effect transistors and processes to form same
    Publication number: 20100038713
    Abstract: A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.
    Type: Application
    Filed: August 13, 2008
    Publication date: February 18, 2010
    Inventors: Prashant Majhi, William Tsai, Jack Kavalieros, Ravi Pillarisetty, Benjamin Chu-Kung
  • Multiple-gate transistors and processes of making same
    Publication number: 20100032763
    Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 11, 2010
    Inventors: Ravi Pillarisetty, Jack Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung
  • Method of forming self-aligned low resistance contact layer
    Publication number: 20100035399
    Abstract: Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor and a second precursor to selectively deposit an amorphous semiconductor layer onto each of the source and drain regions. A metal layer is then deposited over the amorphous semiconductor layer on each of the source and drain regions. An annealing process is then performed on the substrate to allow the metal layer to react with amorphous semiconductor layer to form a low resistance contact layer on each of the source and drain regions. The low resistance contact layer on each of the source and drain regions can be formed as either a silicide layer or germanide layer depending on the type of precursors used.
    Type: Application
    Filed: August 11, 2008
    Publication date: February 11, 2010
    Inventors: Willy Rachmady, Jason W. Klaus, Ravi Pillarisetty, Niloy Mukherjee, Jack Kavalieros, Sean King
  • Replacement spacers for mosfet fringe capacatance reduction and processes of making same
    Publication number: 20100025775
    Abstract: A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 4, 2010
    Inventors: Martin Giles, Titash Rakshit, Lucian Shifren, Jack Kavalieros, Willy Rachmady
  • FIELD EFFECT TRANSISTOR WITH METAL SOURCE/DRAIN REGIONS
    Publication number: 20090325350
    Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
    Type: Application
    Filed: May 2, 2008
    Publication date: December 31, 2009
    Inventors: Marko Radosavljevic, Suman Datta, Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Amian Majumdar, Robert S. Chau
  • NOTCHED-BASE SPACER PROFILE FOR NON-PLANAR TRANSISTORS
    Publication number: 20090315101
    Abstract: A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Inventors: Willy Rachmady, Jack Kavalieros
  • CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT
    Publication number: 20090280608
    Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Application
    Filed: November 2, 2006
    Publication date: November 12, 2009
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau