Abstract: A memory device may include an application chip set including a plurality of applications. The memory device may include a chip decoder configured to select one application among the applications in response to input data and a test fuse signal, and output function data so that a function to be performed by the selected application is selected.

Abstract: A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled.

Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.

Abstract: A memory device may include an application chip set including a plurality of applications. The memory device may include a chip decoder configured to select one application among the applications in response to input data and a test fuse signal, and output function data so that a function to be performed by the selected application is selected.

Abstract: A buffer control circuit includes: an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal; and a buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal.

Abstract: A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.

Abstract: A semiconductor apparatus may include an operation signal input selection block configured to output one of either a first operation signal or a second operation signal, as a select signal, in response to an operation select signal. The semiconductor apparatus may include a target code selection block configured to output one of either a first target code or a second target code, as a select code, in response to the operation select signal. The semiconductor apparatus may include an enable signal generation block configured to generate an enable signal when a time corresponding to the select code passes, in response to the select signal. The semiconductor apparatus may include an operation signal output selection block configured to output the enable signal, as one of either a third operation signal or a fourth operation signal, in response to the operation select signal.

Abstract: A semiconductor memory apparatus may include an active control portion configured to generate a preliminary bank active signal and a single bank refresh signal in response to a command, a refresh control signal, and a bank active signal. The semiconductor memory apparatus may also include a signal combination portion configured to enable the bank active signal when either the preliminary bank active signal or the single bank refresh signal is enabled.

Abstract: A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion.

Abstract: A semiconductor apparatus includes a plurality of stack dies which are formed with a predetermined number of channels. The semiconductor apparatus also includes a base die configured to initialize a channel not electrically coupled with the stack dies.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal.

Abstract: A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation.

Abstract: A semiconductor apparatus may include an operation signal input selection block configured to output one of either a first operation signal or a second operation signal, as a select signal, in response to an operation select signal. The semiconductor apparatus may include a target code selection block configured to output one of either a first target code or a second target code, as a select code, in response to the operation select signal. The semiconductor apparatus may include an enable signal generation block configured to generate an enable signal when a time corresponding to the select code passes, in response to the select signal. The semiconductor apparatus may include an operation signal output selection block configured to output the enable signal, as one of either a third operation signal or a fourth operation signal, in response to the is operation select signal.

Abstract: A buffer control circuit includes: an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal; and a buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal.

Abstract: A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled.

Abstract: A semiconductor memory apparatus may include an active control portion configured to generate a preliminary bank active signal and a single bank refresh signal in response to a command, a refresh control signal, and a bank active signal. The semiconductor memory apparatus may also include a signal combination portion configured to enable the bank active signal when either the preliminary bank active signal or the single bank refresh signal is enabled.

Abstract: A stacked semiconductor apparatus includes a plurality of chips which are stacked one upon the other. One chip of the plurality of chips may be configured to generate a plurality of refresh period signals for performing refresh operations within the plurality of chips, and may be configured to transmit the plurality of refresh period signals to the plurality of chips excluding the one chip. The plurality of chips may respectively receive refresh period signals allocated to them according to chip ID signals, and may perform the refresh operations.

Abstract: A semiconductor device including an operation initiation block suitable for sequentially generating a plurality of operation initiation signals at a predetermined time interval in response to an operation initiation source signal, a clock-based signal generation block suitable for generating an operation termination source signal in response to one of the multiple operation initiation signals and a clock, an operation termination block suitable for sequentially generating a plurality of operation termination signals at the predetermined time interval in response to the operation termination source signal, and an operation control block suitable for sequentially generating a plurality of first operation control signals in response to the multiple operation initiation signals and the multiple operation termination signals.

Abstract: A decoding circuit is disclosed, which relates to a technology for changing a decoding structure without changing a circuit structure. A decoding circuit for decoding N input signals to generate output signals corresponding to elements of 2N binary information includes: a controller configured to generate control signals; a decoding unit configured to generate output signals by decoding the N input signals, wherein the number of output signals is controlled in response to the control signals; and a combination unit configured to output a first output signal by logically combining the output signals of the decoding unit.

Abstract: A semiconductor system including a semiconductor integrated circuit or a semiconductor chip, and a method of driving the semiconductor system are described. The semiconductor integrated circuit includes a plurality of semiconductor chips, at least one first chip through via suitable for penetrating through the plurality of semiconductor chips and interfacing a source ID code between the plurality of semiconductor chips, a plurality of second chip through vias suitable for penetrating through the plurality of semiconductor chips and interfacing a plurality of chip selection signals between the plurality of semiconductor chips, wherein the semiconductor chip uses one of chip selection signals as an internal chip selection signal in response to a chip ID code by selecting one of a unique ID code for the semiconductor chip and an alternative ID code for a preset semiconductor chip when the semiconductor chip fails.