Abstract: Provided is an internal voltage generation circuit for generating an internal voltage used in a semiconductor device. The internal voltage generation circuit includes a standby internal voltage generator which is driven during a standby operation and an active operation and supplies a voltage to a core voltage end, a first active internal voltage generator for supplying a voltage to the core voltage end in response to an active signal activated during the active operation, and a second active internal voltage generator which is driven only for a predetermined time period in response to the active signal, and supplies a voltage to the core voltage end.

Abstract: A memory device with global lines being used for other applications when the global lines are not in use is provided. The memory device includes: a plurality of banks; a global input/output line for transferring data input/output signals of the plurality of banks in a normal operation; and a bank selection signal transferring unit for transferring a plurality of test bank selection signals to the plurality of banks in a test mode.

Abstract: A memory device includes a cell area having N+1 unit cell blocks. Each cell block includes M word lines. The N unit cell blocks are each corresponded to a logical cell block address. The one additional unit cell block is added for accessing data with high speed. A tag block receives a row address, senses the logical cell block address in the row address and outputs a physical cell block address based on the logical cell block address and the candidate information. The tag block includes:N+1 unit tag tables corresponding to the N+l unit cell blocks. Each tag block has M number of registers. The M number of registers correspond to M number of word lines of the corresponding unit cell blocks. Each register stores one logical cell block address. The tag block also includes an initialization unit that initializes the N+1 unit tag tables.

Abstract: A semiconductor memory device includes: a core region having a plurality of bank sets for outputting/storing a data in response to an inputted address, wherein each bank set includes one bank, one row address control unit and two column address control units; and a peripheral region having two pad groups, wherein two pad groups are respectively located at the opposite side of the core region.

Abstract: A memory device with global lines being used for other applications when the global lines are not in use is provided. The memory device includes: a plurality of banks; a global input/output line for transferring data input/output signals of the plurality of banks in a normal operation; and a bank selection signal transferring unit for transferring a plurality of test bank selection signals to the plurality of banks in a test mode.

Abstract: Provided is an internal voltage generation circuit for generating an internal voltage used in a semiconductor device. The internal voltage generation circuit includes a standby internal voltage generator which is driven during a standby operation and an active operation and supplies a voltage to a core voltage end, a first active internal voltage generator for supplying a voltage to the core voltage end in response to an active signal activated during the active operation, and a second active internal voltage generator which is driven only for a predetermined time period in response to the active signal, and supplies a voltage to the core voltage end.

Abstract: A semiconductor device for refreshing data stored in a memory device includes a cell area having N+1 number of unit cell blocks, each including M number of word lines which respectively are coupled to a plurality of unit cells; a tag block having N+1 number of unit tag blocks, each storing at least one physical cell block address denoting a row address storing a data; and a control block for controlling the tag block and the predetermined cell block table for refreshing the data in the plurality of unit cells coupled to a word line in response to the physical cell block address.

Abstract: A semiconductor memory device having a high speed for a data transmission includes a plurality of cell blocks, each having a plurality of unit cells for storing data; a plurality of local bit line sense amplifying block, each for sensing and amplifying the data stored in the N number of cell blocks; a global bit line sense amplifying block for latching the data amplified by the local bit line sense amplifying blocks; and a data transferring block for transmitting the data from the local bit line sense amplifying block to the global bit line sense amplifying block.

Abstract: An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs.

Abstract: An apparatus for controlling a refresh cycle in a semiconductor memory device includes a temperature detection controller for generating a detection control signal and a converting control signal; a temperature detection block, which is enabled by the detection control signal, for generating an analog detection voltage in response to a temperature variation; an analog to digital converter, which is enabled by the converting control signal, for converting the analog detection voltage into a digital control code; and a refresh controller for generating a refresh cycle control signal based on the digital control code in order to control the refresh cycle.

Abstract: A semiconductor memory device for an effective data access operation includes a cell area having N+1 number of unit cell blocks, each including M number of word lines, for storing a data in a unit cell corresponding to an inputted address; N+1 number of unit controlling blocks having respective state machines and corresponding to the respective N+1 unit cell blocks for controlling a data restoration that is accessed from a first unit cell block selected from the N+1 unit cell blocks into the first unit cell block or a second unit cell block; and a driving controlling block for controlling the N+1 unit cell blocks so that the N+1 unit controlling means are in one of first to fourth operation states.

Abstract: A semiconductor memory device includes: a memory core area; a plurality of address input pads for transferring addresses; a first address buffer part for receiving the addresses and outputting first addresses; a plurality of multi I/O pads for inputting/outputting data or inputting/outputting addresses/data while multiplexing the addresses/data; a data I/O buffer part for receiving data from the plurality of multi I/O pads and transferring the data to the memory core area or receiving and outputting addresses; a second address buffer part for receiving the addresses from the data I/O buffer part and outputting second addresses; an address multiplexer part for combining the first addresses and the second addresses and outputting data access addresses to the memory core area; and a path control part for controlling the address multiplexer part.

Abstract: An analog DLL device includes a delay model for modeling delay time for buffering the external clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping charges; a loop filter for generating a reference voltage; a voltage control delay line and a tracking digital-analog converter which converts the reference voltage to a digital value; and stores the digital value for keeping the reference voltage safely.

Abstract: A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.

Abstract: An analog-to-digital converter outputs a reliable digital value corresponding to an input analog value without regard to variation of process, temperature and driving voltage.

Abstract: An apparatus for controlling a refresh cycle in a semiconductor memory device includes a temperature detection controller for generating a detection control signal and a converting control signal; a temperature detection block, which is enabled by the detection control signal, for generating an analog detection voltage in response to a temperature variation; an analog to digital converter, which is enabled by the converting control signal, for converting the analog detection voltage into a digital control code; and a refresh controller for generating a refresh cycle control signal based on the digital control code in order to control the refresh cycle.

Abstract: There is provided a semiconductor memory device and a method for driving the same, which is capable of accessing data in a continuous burst mode regardless of locations of accessed data. The semiconductor memory device includes: a first bank including a first word line corresponding to a first row address; and a second bank including a second word line corresponding to a second row address, wherein the second row address is consecutive to the first row address.

Abstract: An analog-to-digital converter outputs a reliable digital value corresponding to an input analog value without regard to variation of process, temperature and driving voltage.

Abstract: A semiconductor memory device for an effective data access operation includes a cell area having N+1 number of unit cell blocks, each including M number of word lines, for storing a data in a unit cell corresponding to an inputted address; N+1 number of unit controlling blocks having respective state machines and corresponding to the respective N+1 unit cell blocks for controlling a data restoration that is accessed from a first unit cell block selected from the N+1 unit cell blocks into the first unit cell block or a second unit cell block; and a driving controlling block for controlling the N+1 unit cell blocks so that the N+1 unit controlling means are in one of first to fourth operation states.

Abstract: A semiconductor memory device includes: a core region having a plurality of bank sets for outputting/storing a data in response to an inputted address, wherein each bank set includes one bank, one row address control unit and two column address control units; and a peripheral region having two pad groups, wherein two pad groups are respectively located at the opposite side of the core region.