Abstract: A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion.

Abstract: A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.

Abstract: A semiconductor device including an operation initiation block suitable for sequentially generating a plurality of operation initiation signals at a predetermined time interval in response to an operation initiation source signal, a clock-based signal generation block suitable for generating an operation termination source signal in response to one of the multiple operation initiation signals and a clock, an operation termination block suitable for sequentially generating a plurality of operation termination signals at the predetermined time interval in response to the operation termination source signal, and an operation control block suitable for sequentially generating a plurality of first operation control signals in response to the multiple operation initiation signals and the multiple operation termination signals.

Abstract: A semiconductor apparatus includes a plurality of stack dies which are formed with a predetermined number of channels. The semiconductor apparatus also includes a base die configured to initialize a channel not electrically coupled with the stack dies.

Abstract: A stacked semiconductor apparatus includes a plurality of chips which are stacked one upon the other. One chip of the plurality of chips may be configured to generate a plurality of refresh period signals for performing refresh operations within the plurality of chips, and may be configured to transmit the plurality of refresh period signals to the plurality of chips excluding the one chip. The plurality of chips may respectively receive refresh period signals allocated to them according to chip ID signals, and may perform the refresh operations.

Abstract: A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation.

Abstract: A semiconductor integrated circuit includes a plurality of dies, wherein each of the dies is configured to enable a power circuit provided therein according to a power control signal, in a state in which the die was determined to be a good die or a fail die.

Abstract: A semiconductor chip includes an internal voltage generation circuit suitable for generating an internal voltage having a predetermined level, a target internal circuit suitable for performing a predetermined operation using the internal voltage, and a control circuit suitable for checking operating speed of the target internal circuit based on an operation result signal generated from the target internal circuit, and generating the control signal based on the checked operating speed, wherein a voltage level of the internal voltage for target internal circuit is controlled based on the control signal.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.

Abstract: A multi-chip package having a plurality of slice chips coupled through a through-via, at least one slice chip may include an input unit suitable for receiving a slice activation signal, and outputting the slice activation signal to the through-via in response to a slice identification corresponding to the slice chip, a first output unit suitable for outputting the activation signal transferred through the through-via to an internal circuit of the slice chip in response to the corresponding slice identification, and a second output unit suitable for selectively outputting the activation signal transferred through the through-via to the internal circuit of the slice chip in a predetermined activation mode for the multi-chip package.

Abstract: A package includes a master chip including a storage circuit configured to store an impedance setting of the master chip and an impedance setting of a slave chip, and a termination circuit for an impedance matching with an outside of the package, and the slave chip connected to the master chip, wherein if a termination operation for the slave chip is activated, the termination circuit of the master chip performs an impedance matching operation using the impedance setting for the slave chip.

Abstract: A semiconductor system including a semiconductor integrated circuit or a semiconductor chip, and a method of driving the semiconductor system are described. The semiconductor integrated circuit includes a plurality of semiconductor chips, at least one first chip through via suitable for penetrating through the plurality of semiconductor chips and interfacing a source ID code between the plurality of semiconductor chips, a plurality of second chip through vias suitable for penetrating through the plurality of semiconductor chips and interfacing a plurality of chip selection signals between the plurality of semiconductor chips, wherein the semiconductor chip uses one of chip selection signals as an internal chip selection signal in response to a chip ID code by selecting one of a unique ID code for the semiconductor chip and an alternative ID code for a preset semiconductor chip when the semiconductor chip fails.

Abstract: A multi-chip package having a plurality of slice chips coupled through a through-via, at least one slice chip may include an input unit suitable for receiving a slice activation signal, and outputting the slice activation signal to the through-via in response to a slice identification corresponding to the slice chip, a first output unit suitable for outputting the activation signal transferred through the through-via to an internal circuit of the slice chip in response to the corresponding slice identification, and a second output unit suitable for selectively outputting the activation signal transferred through the through-via to the internal circuit of the slice chip in a predetermined activation mode for the multi-chip package.

Abstract: An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.

Abstract: A semiconductor integrated circuit includes a semiconductor chip or a plurality of semiconductor chip stacked therein, wherein each semiconductor chip includes, a compatible mode selection unit configured to select a chip allocation signal allocated to the semiconductor chip, among a plurality of chip allocation signals inputted through a plurality of pads, in response to a stack package information, and an internal circuit configured to perform a given operation in response to the chip allocation signal selected by the compatible mode selection unit.

Abstract: A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.

Abstract: A semiconductor memory apparatus includes one or more semiconductor chips configured to have predetermined capacity and structure; and a signal level control unit configured to control levels of external signals, which are input to the one or more semiconductor chips, in order to realize various capacities and structures using the one or more semiconductor chips.

Abstract: An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.

Abstract: A semiconductor memory apparatus includes a first chip including a refresh signal generation unit which is configured to receive an external command and generate a refresh signal; and a second chip including a first delay unit which is configured to receive the refresh signal through a first through-silicon via and delay the received refresh signal, a first selection unit which is configured to output an output signal of the first delay unit to the first chip through a second through-silicon via in response to a first select signal, and a first core region which is configured to receive the output signal of the first delay unit and perform a refresh operation.