Abstract: A precharge signal generation circuit of a semiconductor memory apparatus may comprise a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command; and a read/write bank precharge address generation section configured to delay a bank column address strobe signal by a second delay time set in response to the precharge command delayed in the read/write precharge command generation section, and generate one of a read bank precharge address and a write bank precharge address.

Abstract: A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.

Abstract: Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature, generating an N-bit digital signal based on the temperature controlled voltage, and generating a refresh signal whose frequency is determined by the N-bit digital signal. The generation of the temperature controlled voltage includes generating a first current that is increased when the measured temperature is decreased and is decreased with the measured temperature is increased, and generating the temperature controlled voltage.

Abstract: A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.

Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.

Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.

Abstract: A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate internal column commands.

Abstract: An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses.

Abstract: Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

Abstract: In one embodiment, an external signal input circuit of a semiconductor memory may include: an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration.

Abstract: An address delay circuit of a semiconductor memory apparatus includes a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output external address as the first delayed address; a control clock input selecting delay block configured to receive the clock as a second control clock in response to a second input control signal, select whether to receive the external address or the first delayed address in response to the first input control signal, and output the selected address as the second delayed address; and a control clock input/output selecting delay block configured to receive the clock, select whether to receive the external address or the second delayed address in response to the second input control signal, and output the selected address as an internal address.

Abstract: A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic.

Abstract: A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.

Abstract: A semiconductor memory device, which performs a refresh operation, includes: a temperature sensing unit for measuring temperature and for generating a temperature controlled voltage and a reference current based on the measured temperature; an analog-digital conversion unit for converting the temperature controlled voltage to an N-bit digital signal; a refresh control unit for generating a refresh signal in response to the N-bit digital signal, wherein, a period of the refresh signal is controlled based on the N-bit digital signal.

Abstract: A delay circuit of a semiconductor memory apparatus includes a decoding unit configured to decode a plurality of test signals and enable one of a plurality of control signals; a bias voltage generation unit configured to generate a first bias voltage and a second bias voltage depending upon the control signal enabled among the plurality of control signals; and a delay unit configured to determine a delay time depending upon levels of the first and second bias voltages, delay an input signal by the determined delay time, and output a resultant signal as an output signal.

Abstract: Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

Abstract: A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.

Abstract: A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.

Abstract: Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

Abstract: A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.