Abstract: Disclosed herein are organic memory devices and methods for fabricating such devices. The organic memory devices comprise a first electrode, a second electrode and an organic active layer extending between the first and second electrodes wherein the organic active layer is formed from one or more electrically conductive organic materials that contain heteroatoms and which are configured in such a manner as that the heteroatoms are available for linking or complexing metal atoms within the organic active layer. The metal ions may then be reduced to form metal filaments within the organic active layer to form a low resistance state and the metal filaments may, in turn, be oxidized to form a high resistance state and thereby function as memory devices.

Abstract: A polymer blend including a first polymer having a unit represented by Formula 1 and a second polymer having a unit represented by Formula 2: wherein in Formulae 1 and 2, R1 through R13, l, and m are the same as defined in the detailed description.

Abstract: A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

Abstract: Disclosed are a method for forming an organic layer pattern which is characterized by forming a thin layer by coating a coating solution including a polyimide-based polymer having a heteroaromatic pendant group including a heteroatom in its polyimide major chain, a photoinitiator and a crosslinking agent on a substrate and drying the substrate, and exposing and developing the thin layer, an organic layer pattern prepared by the method, and an organic memory device comprising the pattern. According to example embodiments, a high-resolution micropattern may be formed without undergoing any expensive process, e.g., photoresist, leading to simplification of the preparation process and cost reduction.

Abstract: A semiconductor memory device includes a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells, and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

Abstract: A polymer and an organic light-emitting device including the same, wherein the polymer has a polymeric unit represented by Formula 1 below:

Abstract: A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

Abstract: A solar light concentration plate comprises a first hologram which receives solar light and diffracts incident light in a range of an incident angle, and first and second light guides respectively disposed on both sides of the first hologram, wherein at least one of the first and second light guides has an outer surface substantially inclined to an inner surface of the at least one of the first and second light guides.

Abstract: An organic memory device having a memory active region formed by an embossing structure. This invention provides an organic memory device including a substrate, a first electrode formed on the substrate, an organic memory layer formed on the first electrode, a second electrode formed on the organic memory layer and an embossing structure provided at the organic memory layer to form a memory active region.

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract: Disclosed herein are an organic memory device and a method for fabricating the device. The organic memory device may include a first electrode, a second electrode and an organic active layer wherein the organic active layer includes an upper organic material layer formed of an electrically conductive organic material containing heteroatoms and a lower organic material layer formed of an electrically non-conductive organic material containing heteroatoms. Because the organic memory device exhibits improved thermal stability and non-volatility, it may be well suited for use in nonvolatile large-capacity storage units. Flexible electrodes may be used in the organic memory device to fabricate flexible memory devices.

Abstract: A dendrimer according to example embodiments may include a triphenylamine core, wherein a conjugated dendron having no heteroatoms is coupled to the triphenylamine core. An organic memory device according to example embodiments may include an organic active layer between a first electrode and a second electrode, wherein the organic active layer includes the dendrimer according to example embodiments. A barrier layer may be provided between the first and second electrodes. A method of manufacturing the organic memory device according to example embodiments may include forming an organic active layer between a first electrode and a second electrode, the organic active layer including the dendrimer according to example embodiments.

Abstract: A solar light concentration plate comprises a plurality of holograms diffracting incident light wherein each of the plurality of the holograms has a thickness, at least one intermediate light guide plate disposed between the plurality of the holograms, and a pair of external light guide plates disposed on outer surfaces of outermost holograms of the plurality of the holograms, wherein at least one of the pair of the external light guide plates has an inner surface and an outer surface inclined relative to the inner surface.

Abstract: A method of fabricating a three-dimensional semiconductor memory device includes providing a substrate which includes a cell array region and a peripheral region. The method further includes a peripheral structure on the peripheral region of the substrate, where the peripheral structure includes peripheral circuits and is configured to expose the cell array region of the substrate. The method further includes forming a lower cell structure on the cell array region of the substrate, forming an insulating layer to cover the peripheral structure and the lower cell structure on the substrate, planarizing the insulating layer using top surfaces of the peripheral structure and the lower cell structure as a planarization stop layer, and forming an upper cell structure on the lower cell structure.

Abstract: Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.

Abstract: A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

Abstract: Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.

Abstract: Disclosed herein is a dendrimer, in which metallocene, which is an oxidation-reduction material, is located at a core, and a conjugated dendron is connected to the metallocene core by a linker compound, an organic active layer having the dendrimer, an organic memory device having the organic active layer and a method of manufacturing the organic active layer and the organic memory device. The organic memory device manufactured using a dendrimer having a metallocene core of example embodiments may have a shorter switching time, decreased operation voltage, decreased manufacturing cost and increased reliability, thereby realizing a highly-integrated large-capacity memory device.

Abstract: Example embodiments herein relate to compositions useful in forming organic active patterns that may, in turn, be incorporated in organic memory devices. The compositions comprise N-containing conjugated electroconductive polymer(s), photoacid generator(s) and organic solvent(s) capable of dissolving suitable quantities of both the electroconductive polymer and the photoacid generator. Also disclosed are methods for patterning organic active layers formed using one or more of the compositions to produce organic active patterns, portions of which may be arranged between opposed electrodes to provide organic memory cells. The methods include directly exposing and developing the organic active layer to obtain fine patterns without the use of a separate masking pattern, for example, a photoresist pattern, thereby tending to simplify the fabrication process and reduce the associated costs.

Abstract: The present invention relates to a negative pulse transient signal analysis methods and negative pulse transient signal analysis module for a PC base simulation equivalent circuit capable of grasping and improving error causes through an abnormal signal analysis after configuring a simulation equivalent circuit for a 4˜20 mA instrument unsatisfied in a temperature environmental impact assessment.