Patents by Inventor Jae Joo

Jae Joo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DEVICE AND METHOD FOR INSPECTING A SEALING MEMBER
    Publication number: 20150022652
    Abstract: A sealing inspection device includes a scan unit through which a display device substrate including a top plate coupled to a bottom plate by a sealing member in the sealed area passes; and a photographing unit through which the display device substrate which has passed through the scan unit, further passes. The scan unit generates coordinate values of the sealed area of the display device substrate, detects a defective region in the sealed area of the display device substrate, and includes a plurality of scan cameras. The photographing unit generates an image of the sealed area of the display device substrate using the generated coordinate values, measures an effective sealing width of the sealed area using the generated image, and comprises a measuring camera.
    Type: Application
    Filed: December 19, 2013
    Publication date: January 22, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventor: Wan-Jae JOO
  • Three-dimensional semiconductor devices
    Patent number: 8921918
    Abstract: Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Joo Shim, Kyoung-Hoon Kim, Woonkyung Lee, Wonseok Cho, Hoosung Cho, Jintaek Park, Jong-Yeon Kim, Sung-Min Hwang
  • A/V parental lock apparatus and method
    Patent number: 8914823
    Abstract: Provided are an apparatus and method for restricting A/V listening and viewing using parental levels. According to an embodiment of the present invention, a parental level detected from a video signal is compared with a level set by a user, and previously buffered video and audio are repeatedly output if the detected parental level is higher than the level set by the user. The parental level is included and transmitted in a video line of a broadcast signal. Also, the repeatedly output video is a still image or a moving image, and the repeatedly output audio is audio between two audio mute periods finally detected. Accordingly, there is no case when a user waits for nothing while viewing a black screen in a mute state, while a parental lock operation is performed.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: December 16, 2014
    Assignee: Humax, Co., Ltd.
    Inventor: Jae Joo Kim
  • PASSIVE CONTAINMENT SPRAY SYSTEM
    Publication number: 20140334591
    Abstract: Provided is a passive containment spray system including: a spray coolant storage unit that communicates with a containment accommodating a reactor vessel and maintains equilibrium of pressure between the spray coolant storage unit and the containment; a spray pipe that is installed within the containment in such a manner that when an accident occurs, a coolant supplied from the spray coolant storage unit is sprayed into the containment through the spray pipe due to an increase in pressure within the containment; and a connection pipe one end of which is inserted into the spray coolant storage unit in such a manner as to provide a flow path along which the coolant flows and the other end of which is connected to the spray pipe in such a manner that the coolant is passively supplied to the spray pipe through the connection pipe therein.
    Type: Application
    Filed: May 7, 2014
    Publication date: November 13, 2014
    Applicant: KOREA ATOMIC ENERGY RESEARCH INSTITUTE
    Inventors: Young In KIM, Soo Jai SHIN, Han Ok KANG, Keung Koo KIM, Ju Hyeon YOON, Tae Wan KIM, Jae Joo HA
  • COOLING SYSTEM OF EMERGENCY COOLING TANK AND NUCLEAR POWER PLANT HAVING THE SAME
    Publication number: 20140334590
    Abstract: The present disclosure provides a cooling system of an emergency cooling tank, which enables long-term cooling without refilling cooling water, in case of the change in a quantity of heat transferred to the emergency cooling tank according to a lapse of time upon an occurrence of an accident of a nuclear reactor, and a nuclear power plant having the same.
    Type: Application
    Filed: May 6, 2014
    Publication date: November 13, 2014
    Applicant: KOREA ATOMIC ENERGY RESEARCH INSTITUTE
    Inventors: Young In KIM, Keung Koo KIM, Young Min BAE, Ju Hyeon YOON, Jae Joo HA, Won Jae LEE, Tae Wan KIM
  • Vertical nonvolatile memory devices having reference features
    Patent number: 8836020
    Abstract: A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ld.
    Inventors: Ju-young Lim, Woon-kyung Lee, Jae-joo Shim, Hui-chang Moon, Sung-min Hwang
  • THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20140248766
    Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.
    Type: Application
    Filed: May 13, 2014
    Publication date: September 4, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JAE-JOO SHIM, Hansoo Kim, Wonseok Cho, Jaehoon Jang, Woojin Cho
  • Three dimensional semiconductor memory devices
    Patent number: 8809938
    Abstract: Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Sung-Min Hwang, Hansoo Kim, Changseok Kang, Wonseok Cho, Jae-Joo Shim
  • Semiconductor memory device comprising three-dimensional memory cell array
    Patent number: 8787082
    Abstract: A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoungkeun Son, Hansoo Kim, Youngsoo An, Mingu Kim, Jinho Kim, Jaehyoung Choi, Sukhun Choi, Jae-Joo Shim, Wonseok Cho, Sunil Shim, Ju-Young Lim
  • Organic light emitting device and method of manufacturing the same
    Patent number: 8749132
    Abstract: An organic light emitting device (“OLED”) including a substrate; a plurality of polymer beads disposed on a substrate; a light emitting layer covering the plurality of polymer beads and having an embossed structure; and a cathode disposed on the light emitting layer.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-jae Joo, Jhun-mo Son, Hye-yeon Yang
  • Three-dimensional semiconductor device including a mold structure providing gap regions and an interconnection structure including a plurality of interconnection patterns formed in the gap regions
    Patent number: 8742466
    Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Joo Shim, Hansoo Kim, Wonseok Cho, Jaehoon Jang, Woojin Cho
  • SEMICONDUCTOR DEVICES
    Publication number: 20140048873
    Abstract: A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.
    Type: Application
    Filed: October 18, 2013
    Publication date: February 20, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Joo SHIM, Han-Soo KIM, Won-Seok CHO, Jae-Hoon JANG, Sang-Yong PARK
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICE
    Publication number: 20140048850
    Abstract: According to example embodiments, a semiconductor device may include a high electron mobility transistor (HEMT) on a first region of a substrate, and a diode on a second region of the substrate. The HEMT may be electrically connected to the diode. The HEMT and the diode may be formed on an upper surface of the substrate such as to be spaced apart from each other in a horizontal direction. The HEMT may include a semiconductor layer. The diode may be formed on another portion of the substrate on which the semiconductor layer is not formed. The HEMT and the diode may be cascode-connected to each other.
    Type: Application
    Filed: March 8, 2013
    Publication date: February 20, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo-chul JEON, Young-hwan PARK, Ki-yeol PARK, Jai-kwang SHIN, Jae-joo OH, Jong-bong HA
  • Photosensitive quantum dot, composition comprising the same and method of forming quantum dot-containing pattern using the composition
    Patent number: 8642991
    Abstract: A photosensitive quantum dot including a quantum dot, and a plurality of photosensitive moieties that are bound to a surface of the quantum dot, wherein each of the photosensitive moieties includes silicon (Si) and a photosensitive functional group. Also disclosed are a composition for forming a quantum dot-containing pattern, where the composition includes the photosensitive quantum dot, and a method of forming a quantum dot-containing pattern using the composition.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-jin Park, Kwang-hee Lee, Won-jae Joo, Xavier Bulliard, Yun-hyuk Choi, Kwang-sup Lee
  • Semiconductor device and method of fabricating the same
    Patent number: 8592912
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Hansoo Kim, Wonseok Cho, Jaehoon Jang, Jae-Joo Shim
  • Photosensitive compositions useful for forming active patterns, methods of forming such active patterns and organic memory devices incorporating such active patterns
    Patent number: 8580484
    Abstract: Example embodiments herein relate to compositions useful in forming organic active patterns that may, in turn, be incorporated in organic memory devices. The compositions comprise N-containing conjugated electroconductive polymer(s), photoacid generator(s) and organic solvent(s) capable of dissolving suitable quantities of both the electroconductive polymer and the photoacid generator. Also disclosed are methods for patterning organic active layers formed using one or more of the compositions to produce organic active patterns, portions of which may be arranged between opposed electrodes to provide organic memory cells. The methods include directly exposing and developing the organic active layer to obtain fine patterns without the use of a separate masking pattern, for example, a photoresist pattern, thereby tending to simplify the fabrication process and reduce the associated costs.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Kyun Lee, Won Jae Joo, Kwang Hee Lee, Tae Lim Choi, Myung Sup Jung
  • Manufacturing semiconductor devices
    Patent number: 8563378
    Abstract: A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Joo Shim, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang, Sang-Yong Park
  • Polymer and organic light emitting device including polymer
    Patent number: 8558007
    Abstract: A polymer and an organic light-emitting device including the polymer are provided, wherein the polymer comprises a polymeric unit represented by the Formula: In which variables are as defined herein.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-yeon Yang, Won-jae Joo, Jhun-mo Son, Ho-suk Kang
  • Volatile negative differential resistance device using metal nanoparticles
    Patent number: 8546789
    Abstract: Disclosed herein is a volatile negative differential resistance device using metal nanoparticles, the device includes an organic layer disposed between two metal electrodes, in which the organic layer includes uniformly dispersed metal nanoparticles having a diameter of about 10 nm or less in an organic material. The device of this invention exhibits a volatile negative differential resistance phenomenon at room temperature upon application of a voltage and is thus suitable for use in various switching devices and logic devices, with excellent reproducibility and simple inexpensive processing.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Jae Joo, Kwang Hee Lee, Sang Kyun Lee, Chulhee Kim
  • Semiconductor device and method of forming the same
    Patent number: 8519472
    Abstract: A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: August 27, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehun Jeong, Ju-Young Lim, Hansoo Kim, Jaehoon Jang, Sunil Shim, Jae-Joo Shim