Abstract: A liquid crystal display device is disclosed. The disclosed liquid crystal display device includes gate lines, data lines formed to intersect with the gate lines, thereby defining sub-pixel regions, vertical common lines formed in parallel to the data lines such that at least one vertical common line is arranged for one pixel region, which is constituted by at least three sub-pixel regions, thin film transistors each connected to a corresponding one of the gate lines and a corresponding one of the data lines, pixel electrodes each connected to a corresponding one of the thin film transistors, and common electrodes each connected to a corresponding one of the vertical common lines.

Abstract: Disclosed are cis-2,6-disubstituted tetrahydropyran derivatives represented by Chemical Formula 1 and a preparation method thereof. The tetrahydropyran derivatives can be prepared by Prins-reacting tetrahydropyran derivatives with homopargylicalcohol derivatives in the presence of trimethylsilyltriflate. The tetrahydropyran derivatives with cis-substituents at both C2 and C6 positions of the tetrahydropyran ring are useful as intermediates for use in the synthesis and development of therapeutically effective, naturally occurring compounds. (wherein, R1, R2 and R3 are as defined in the specification.

Abstract: A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.

Abstract: According to an embodiment, a fabrication method includes forming a gate line disposed along a first direction and a common line parallel to the gate line on a substrate, the gate and common lines spaced apart from each other, forming a gate insulating layer on the gate and common lines, forming a semiconductor layer on the gate insulating layer, forming a source electrode and a pixel electrode of transparent conductive material, the pixel electrode including a drain electrode portion, the drain electrode portion overlapping the semiconductor layer, forming a passivation layer including a first contact hole and an open portion, the first contact hole exposing the source electrode and the open portion exposing the pixel electrode, respectively, and forming a data line disposed along a second direction on the passivation layer, the data line connected to the source electrode through the first contact hole and crossing the gate line.

Abstract: The present invention relates to novel anthranilic acid derivatives represented by Chemical Formula I, and a chloride channel blocking agent containing the anthranilic acid derivative or its pharmacologically acceptable salts as an active ingredient. In another aspect, the present invention relates to a method of accurately and efficiently detecting the intracellular chloride channel inhibition and method of screening a chloride channel blocking agent.

Abstract: A method for forming a contact in a semiconductor device, comprises providing a substrate, forming a plurality of conductive patterns and a passivation layer surrounding the conductive patterns over the substrate, forming an insulation layer covering the conductive patterns and passivation layer, forming a mask pattern for a contact over the insulation layer, forming a first opening by performing an isotropic etch process on the insulation layer using the mask pattern as an etch mask, wherein the isotropic etch process is performed until the insulation layer meets the passivation layer, forming a barrier layer over a resultant structure of the first opening, exposing the insulation layer by performing an anisotropic etch process using the mask pattern as an etch mask, and forming a second opening exposing the substrate by performing a self aligned contact (SAC) process using the mask pattern and barrier layer as an etch mask.

Abstract: A liquid crystal display device includes a first substrate and a second substrate facing each other; a gate line and a data line crossing each other to define a pixel region on the first substrate; a thin film transistor on the first substrate and adjacent to the pixel region; a column spacer located on the second substrate; a protrusion located on the first substrate at a location corresponding to the protrusion, the protrusion having a hollow portion and a surrounding wall surrounding the hollow portion, the hollow portion being exposed at the top side of the protrusion; and a liquid crystal layer interposed between the first substrate and the second substrate.

Abstract: An array substrate for a liquid crystal display device includes a transparent substrate, a gate line arranged along a first direction on the transparent substrate, a gate electrode extending from the gate line, a common line arranged along the first direction adjacent to the gate line and having a protrusion, a gate insulation layer on the transparent substrate to cover the gate line, the gate electrode, and the common electrode, an active layer on the gate insulation layer and over the gate electrode, first and second ohmic contact layers on the active layer, a data line arranged along a second direction perpendicular to the first upon the gate insulation layer, a source electrode extending from the data line and contacting the first ohmic contact layer, a drain electrode spaced apart from the source electrode and contacting the second ohmic contact layer, a first capacitor electrode formed on the gate insulation layer and connected to the drain electrode, the first capacitor electrode overlapping the common

Abstract: A liquid crystal display device includes a display panel including a display area and a non-display area surrounding the display area, a plurality of gate lines and data lines arranged on the display area to intersect each other, so as to define a plurality of pixel regions, a plurality of thin-film transistors formed at respective intersections of the gate lines and the data lines, a plurality of pixel electrodes formed on the respective pixel regions and connected to the thin film transistors, and at least one first common line provided between the data lines and arranged parallel to the data lines.

Abstract: Trenches in a semiconductor substrate are filled by (i) dispensing a film forming material on the semiconductor substrate and into the trenches; (ii) curing the dispensed film forming material in the presence of an oxidant at a first low temperature for a first predetermined period of time; (iii) curing the dispensed film forming material in the presence of an oxidant at a second low temperature for a second predetermined period of time; (iv) curing the dispensed film forming material in the presence of an oxidant at a third high temperature for a third predetermined period of time; and (v) forming filled oxide trenches in the semiconductor substrate. The film forming material is hydrogen silsesquioxane.

Abstract: An array substrate for a liquid crystal display device includes a transparent substrate, a gate line arranged along a first direction on the transparent substrate, a gate electrode extending from the gate line, a common line arranged along the first direction adjacent to the gate line and having a protrusion, a gate insulation layer on the transparent substrate to cover the gate line, the gate electrode, and the common electrode, an active layer on the gate insulation layer and over the gate electrode, first and second ohmic contact layers on the active layer, a data line arranged along a second direction perpendicular to the first upon the gate insulation layer, a source electrode extending from the data line and contacting the first ohmic contact layer, a drain electrode spaced apart from the source electrode and contacting the second ohmic contact layer, a first capacitor electrode formed on the gate insulation layer and connected to the drain electrode, the first capacitor electrode overlapping the common

Abstract: The present invention shows that an in-plane switching mode LCD and a method for fabricating the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.

Abstract: An LCD device and a method for manufacturing the same is disclosed, in which it is possible to correct a problem of insufficient or excessive supply of liquid crystal in an LCD device by controlling an amount of liquid crystal. The method includes preparing a liquid crystal cell comprised of a first substrate, a second substrate, a liquid crystal layer between the first and second substrates, and a first sealant formed in the periphery of the liquid crystal layer between the first and second substrates; measuring an amount of liquid crystal provided to the inside of liquid crystal cell; forming an inlet for liquid crystal in the first sealant; and regulating the amount of liquid crystal by supplying or discharging the liquid crystal through the inlet; and sealing the inlet.

Abstract: A method for driving an IPS mode LCD device prevents leakage current by swing of a common voltage. The IPS mode LCD device includes multiple gate and data lines crossing each other to define a plurality of pixel regions, multiple thin film transistors (TFT) alternately positioned at lower and upper side pixel regions adjacent to the corresponding gate line, and multiple common lines in a zigzag type along the thin film transistors in the pixel regions. A common voltage is applied so that a first common voltage or a second common voltage is inversely applied to even numbered common lines or odd numbered common lines in one vertical period to be synchronized with a scanning signal supplied to the first gate line, and a gate Low voltage applied to each gate line is lower than a pixel voltage on transition of the common voltage from “High” to “Low”.

Abstract: A liquid crystal display device having thin film transistors arranged in a zigzag pattern at opposite sides of a gate line, and method for fabricating the same to prevent occurrence of a Cgd variation, even when gate lines or data lines are misaligned in Y- or Z-axis direction, and a defective interface caused by stitching. The device includes a plurality of gate lines arranged on a substrate in one direction, a plurality of data lines substantially perpendicular to the gate lines to define pixel regions, and one pair of thin film transistors per pixel region, the pair of thin film transistors including one pair of first and second gate electrodes projected from the gate lines, a drain electrode substantially parallel to the gate lines, having opposite ends overlapping the first and second gate electrodes, and a source electrode projected from the data lines so as to be adjacent to the opposite ends of the drain electrode and overlap the first and second gate electrodes.

Abstract: A liquid crystal display apparatus and a method of driving the same capable of lowering a power consumption as well as a production cost. A liquid crystal display apparatus according to the present invention comprises: pixels including red, green and blue color pixels arranged in a direction along a data line; gate line groups, each gate line group having a set of two gate lines electrically connected each other, and each gate line crossing the data line; a data driver that drives the data line; a gate driver that drives the gate line groups; and a timing controller that controls the data driver and the gate driver, the timing controller having at least one line memory that temporarily stores data supplied to the data driver.

Abstract: A method for fabricating a semiconductor device includes forming a fuse over a substrate, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, selectively removing the anti-reflective layer, forming an insulation layer over a whole surface of the resultant structure including the fuse, and performing repair-etching such that part of the insulation layer remains above the fuse.

Abstract: According to an embodiment, a fabrication method includes forming a gate line disposed along a first direction and a common line parallel to the gate line on a substrate, the gate and common lines spaced apart from each other, forming a gate insulating layer on the gate and common lines, forming a semiconductor layer on the gate insulating layer, forming a source electrode and a pixel electrode of transparent conductive material, the pixel electrode including a drain electrode portion, the drain electrode portion overlapping the semiconductor layer, forming a passivation layer including a first contact hole and an open portion, the first contact hole exposing the source electrode and the open portion exposing the pixel electrode, respectively, and forming a data line disposed along a second direction on the passivation layer, the data line connected to the source electrode through the first contact hole and crossing the gate line.

Abstract: A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.

Abstract: A method for driving an In-Plane switching (IPS) mode LCD device is disclosed. The IPS mode LCD device includes gate and data lines crossing each other to define pixel regions; thin film transistors (TFTs) alternately positioned at lower and upper side pixel regions adjacent to the corresponding gate lines; and common lines of a zigzag type along the thin film transistors in the pixel regions. A common voltage is applied, wherein a first common voltage or a second common voltage is inversely applied to even numbered common lines or odd numbered common lines in one vertical period to be synchronized with a scanning signal supplied to the first gate line, and a gate Low voltage supplied to each gate line is classified into 2 levels, and inverted in synchronization with the common voltage, thereby improving the coupling of a pixel voltage on swing of a common voltage.