Abstract: Embodiments of a semiconductor device and a method of fabricating the same may include an insulating layer formed on a substrate and having a predetermined hole, a metal interconnection formed in the hole and protruding relative to the insulating layer, a first barrier extending in a lateral direction of the metal interconnection, a second barrier formed on the metal interconnection, and a metal pad formed on the second barrier.

Abstract: Disclosed herein is a metal enolate initiator for polymerizing isocyanates and a method for polymerizing isocyanates by anionic polymerization using the same, in which the initiator forms a cluster upon the initiation and protects stability of terminal anions at the end of the chain to cause controlled polymerization, thus preventing depolymerizaton and improving reaction time and efficiency without the use of a separate additive.

Abstract: Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthenium oxide layer and a second ruthenium layer, a seed copper layer formed on the barrier metal layer, and a copper line layer made of a Cu—Ag—Au solid solution. A disclosed example method of manufacturing a semiconductor device reduces and/or prevents contact characteristic degradation of the barrier metal layer with the silicon substrate or the damascene insulating layer. In addition, by forming the copper line layer made of the Cu—Ag—Au solid solution, long term device reliability may be improved.

Abstract: The present invention relates to terphenyl dihydroxy monomers containing fluorine and fluorinated poly(arylene ether sulfide)s prepared by using the monomers, more particularly, terphenyl dihydroxy monomers containing both two hydroxy functional groups and fluorine and fluorinated poly(arylene ether sulfide)s prepared by an aromatic nucleophilic substitution polymerization (SNAr) using the monomers, which are thus useful as optical materials in the field of information telecommunications.

Abstract: A sulfonated poly(arylene ether) copolymer that has a crosslinking structure in a chain of a polymer, a sulfonated poly(arylene ether) copolymer that has a crosslinking structure in and at an end of a chain of a polymer, and a polymer electrolyte film that is formed by using them are disclosed. According to the polycondensation reaction of the sulfonated dihydroxy monomer (HO—SAr1-OH), the none sulfonated dihydroxy monomer (HO—Ar—OH), the crosslinkable dihalide monomer (X—CM-X) and the none sulfonated dihalide monomer (X—Ar—X), the poly(arylene ether) copolymer in which the sulfonic acid is included is synthesized. The formed poly(arylene ether) copolymer has the crosslinkable structure in the chain of the polymer. In addition, by carrying out the polycondensation reaction in respects to the crosslinkable monohydroxy monomer or the crosslinkable monohalide monomer, the crosslinking can be formed at the end of the polymer.

Abstract: An anionic polymerization method for styrene derivative containing pyridine as functional group is provided. The method includes forming a complex of (vinylphenyl)-pyridine and lithium chloride and performing anionic polymerization. Accordingly, a polymer of styrene derivative containing pyridine can be obtained. The polymer has excellent optical properties, and its molecular weight and molecular weight distribution can be controlled.

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. In a disclosed method, a dangling bond in the active region(s) is removed by providing an enough H2 in the PMD liner layer and the interlayer insulating layer directly contacting the active regions, and then gradually diffusing the H2 in a subsequent heat treatment. The method includes forming a gate electrode having a side wall spacer, forming source and drain regions, forming a PMD liner layer by sequentially forming a SiO2:H layer, a SiON:H layer and a SiN:H layer above the gate electrode and the source and drain regions, forming an interlayer insulating layer above the PMD liner layer, and diffusing hydrogen in the PMD liner layer and the interlayer insulating layer to the source and drain region by N2 annealing or Ar annealing.

Abstract: Provided are a vinyl-biphenylpyridine monomer and a polymer thereof. More particularly, the present invention provides a vinyl-biphenylpyridine monomer having a side chain of pyridine or phenylpyridine as a functional group, a homopolymer of which molecular weight and molecular weight distribution are controlled using the monomer, and a block copolymer of which molecular structure and molecular weight are controlled to facilitate synthesis of an organic metal complex. Accordingly, the present invention provides a vinyl-biphenylpyridine monomer and a polymer thereof which are effectively used as nano and optical functional materials.

Abstract: Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being destroyed due to electro-migration (EM) and stress-migration (SM). An illustrated metal interconnection line includes: a semiconductor substrate; a metal pattern on the substrate; a glue pattern under the metal pattern; an anti-reflection pattern on the metal pattern; and dummy patterns surrounding side walls of the metal pattern.

Abstract: Semiconductor devices to reduce stress on a metal interconnect are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a stress-relief layer formed on the aluminum layer to thereby prevent cracking of the passivation layer during a subsequent packaging process, to increase reliability of the passivation layer, and to prevent degradation of properties of the semiconductor device.

Abstract: A P-type polysilicon layer having a stable and desired resistivity is formed by alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a semiconductor substrate by atomic layer deposition, and thereafter forming a P-type polysilicon layer by thermally diffusing the plurality of group IIIA element atom layers into the plurality of silicon atom layers. The plurality of group IIIA element atom layers may comprise Al, Ga, In, and/or Tl.

Abstract: Semiconductor devices and methods of fabricating the same are disclosed. An illustrated semiconductor device fabricating method includes forming a titanium and titanium-nitride (Ti/TiN) metal layer on a lower oxide layer; forming an aluminum metal layer on the Ti/TiN metal layer; forming an indium tin oxide (ITO) layer on the aluminum metal layer; and patterning the ITO layer, the aluminum metal layer, and the Ti/TiN metal layer by photolithography to form a metal layer pattern and to expose a surface of the lower oxide layer, thereby facilitating a process of filling inter-wiring spaces occurring between adjacent lines of a metal layer pattern by producing a metal layer pattern having a reduced aspect ratio.

Abstract: The present invention relates to a method for preventing a metal corrosion in a semiconductor device. The present method includes the steps of etching of a metal layer in a chamber, the metal layer having a photoresist pattern thereon or thereover; oxidizing a surface of the metal layer using a plasma comprising N2O in the same chamber; and removing the photoresist. Therefore, metal corrosion as well as bridges between metal wirings can be suppressed or prevented, thereby improving the profile of metal layer and the reliability and yield of the semiconductor device.

Abstract: Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthenium oxide layer and a second ruthenium layer, a seed copper layer formed on the barrier metal layer, and a copper line layer made of a Cu—Ag—Au solid solution. A disclosed example method of manufacturing a semiconductor device reduces and/or prevents contact characteristic degradation of the barrier metal layer with the silicon substrate or the damascene insulating layer. In addition, by forming the copper line layer made of the Cu—Ag—Au solid solution, long term device reliability may be improved.

Abstract: Semiconductor devices and methods of fabricating the same are disclosed. An illustrated semiconductor device fabricating method includes forming a titanium and titanium-nitride (Ti/TiN) metal layer on a lower oxide layer; forming an aluminum metal layer on the Ti/TiN metal layer; forming an indium tin oxide (ITO) layer on the aluminum metal layer; and patterning the ITO layer, the aluminum metal layer, and the Ti/TiN metal layer by photolithography to form a metal layer pattern and to expose a surface of the lower oxide layer, thereby facilitating a process of filling inter-wiring spaces occurring between adjacent lines of a metal layer pattern by producing a metal layer pattern having a reduced aspect ratio.

Abstract: The present invention relates to an amphiphilic triblock copolymer comprising a poly(2-vinylpyridine) block and a poly(alkylisocyanate) block and the preparation method thereof, and particularly relates to an amphiphilic triblock copolymer comprising a coil-shaped hydrophilic poly(2-vinylpyridine) block and a rod-shaped lipophilic poly(alkylisocyanate) block, having a controlled structure of coil-rod-coil or rod-coil-rod, and the preparation method thereof.

Abstract: Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthenium oxide layer and a second ruthenium layer, a seed copper layer formed on the barrier metal layer, and a copper line layer made of a Cu—Ag—Au solid solution. A disclosed example method of manufacturing a semiconductor device reduces and/or prevents contact characteristic degradation of the barrier metal layer with the silicon substrate or the damascene insulating layer. In addition, by forming the copper line layer made of the Cu—Ag—Au solid solution, long term device reliability may be improved.

Abstract: A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes forming a photoresist pattern for ion implantation, implanting ions into the aluminum layer, and annealing by using a rapid thermal process.

Abstract: Disclosed are a monomer of iridium complex having a fluoro group as a functional group, a monomer of carbazole derivative having a hydroxy group as the functional group, and a copolymer containing the monomers in its main chain. The iridium complex used as a phosphorescent material and the carbazole derivative having an excellent hole transporting capability are synthesized as the monomer to form the copolymer. The content of iridium complex is easily controlled, and the carbazole derivative and iridium complex are contained in the main chain during the copolymer formation, thereby capable of manufacturing a light emitting device with higher heat resistance and chemical stability.

Abstract: Methods of forming a shallow trench isolation structures in semiconductor devices are disclosed. A disclosed method comprises forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate; forming a trench defining first and second active areas by etching the second oxide layer, the nitride layer, the first oxide layer, and the substrate in a predetermined area; forming a third oxide layer along an inside of the trench; forming a fourth oxide layer to fill up the trench; forming a sacrificial oxide layer on the fourth oxide layer; and removing the sacrificial oxide layer, the fourth oxide layer, the third oxide layer, the second oxide layer, and the nitride layer so as to form the shallow trench isolation. Thus, it is possible to minimize the damage of a narrow active area when forming an element isolation area through an STI process.