Abstract: A chip antenna includes a radiation portion having a block shape and a first surface and a second surface opposing each other, and configured to receive and radiate a feed signal as an electromagnetic wave; a first block made of a dielectric material and coupled to the first surface of the radiation portion; a second block made of a dielectric material and coupled to the second surface of the radiation portion; a ground portion having a block shape and coupled to the first block, and configured to reflect the electromagnetic wave radiated by the radiation portion back toward the radiation portion; and a director having a block shape and coupled to the second block, wherein an overall width of the ground portion, the first block, and the radiation portion is 2 mm or less, and the first block has a dielectric constant of 3.5 or more to 25 or less.

Abstract: An antenna module includes a substrate having a first surface including a ground region and a feeder region; chip antennas mounted on the first surface of the substrate; and at least one patch antenna disposed inside of the substrate or at least partially disposed on a second surface of the substrate. The chip antennas include a body portion, a ground portion bonded to a first surface of the body portion, and a radiation portion bonded to a second surface of a body portion. The ground portion of each chip antenna is mounted on the ground region and the radiation portion of each chip antenna is mounted on the feeder region.

Abstract: A display device comprises a cover window including a first area of a curved shape and a second area of a flat shape and having a first end connected to the first area, wherein the first area has a plurality of first concave patterns at its inner surface; a display panel under the cover window; and an adhesive layer between the cover window and the display panel.

Abstract: A chip antenna includes: a hexahedral-shaped body portion having a permittivity, and including a first surface and a second surface opposite to the first surface; a hexahedral-shaped radiation portion coupled to the first surface of the body portion; and a hexahedral-shaped ground portion coupled to the second surface of the body portion, wherein a width of each of the radiation portion and the ground portion is in a range of 100 ?m to 500 ?m.

Abstract: Disclosed is a battery module. The battery module includes: a battery cell stack in which a plurality of battery cells are stacked; a plurality of end plates at least partially surrounding the battery cell stack; and a support member coupled to the plurality of end plates and supporting the plurality of end plates.

Abstract: A multilayer ceramic capacitor includes an active region including a plurality of dielectric layers, and first and second internal electrodes alternately disposed with each of the dielectric layers interposed therebetween; and upper and lower cover regions including at least one ferromagnetic layer and disposed on and below the active region, respectively.

Abstract: There is further provided a transparent adhesive composition including a silicon acrylate monomer; a silanol compound; an alkoxy silane compound; and an optical initiator.

Abstract: A multilayer ceramic capacitor includes an active region including a plurality of dielectric layers, and first and second internal electrodes alternately disposed with each of the dielectric layers interposed therebetween; and upper and lower cover regions including at least one ferromagnetic layer and disposed on and below the active region, respectively.

Abstract: The present invention related to ferromagnetic nano-metal powders and more particularly, to ferromagnetic nano-metal powders for increasing packing density by decreasing the porosity between micro-sized soft magnetic metal powders. According to an embodiment of the present invention, the ferromagnetic nano-metal powder allows high packing density and high magnetic property at a high frequency to fill the pores inevitably generated during the manufacturing process of an inductor using the soft magnetic metal powders.

Abstract: The present invention related to ferromagnetic nano-metal powders and more particularly, to ferromagnetic nano-metal powders for increasing packing density by decreasing the porosity between micro-sized soft magnetic metal powders. According to an embodiment of the present invention, the ferromagnetic nano-metal powder allows high packing density and high magnetic property at a high frequency to fill the pores inevitably generated during the manufacturing process of an inductor using the soft magnetic metal powders.

Abstract: Provided is a composite for manufacturing a chip part for a high frequency, and the composite includes a magnetic powder having a relatively spherical shape, and a metal magnetic body particle having a relatively more amorphous shape than that of the magnetic powder and a lower hardness than that of the magnetic powder.

Abstract: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

Abstract: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

Abstract: A split-gate flash memory cell and a manufacturing method thereof is provided. After a tunnel oxide layer is formed over a substrate, a peak floating gate layer of conducting material is formed over a portion of the tunnel oxide layer. An inter-gate insulating layer and a control gate layer are formed over the peak floating gate layer and then the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer are sequentially etched down to generate a control gate, an inter-gate insulating region, a peak floating gate and a tunnel oxide region. Finally, a source and a drain are defined adjoining the tunnel oxide region by using a self-align technique.

Abstract: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

Abstract: A split-gate flash memory cell and a manufacturing method thereof is provided. After a tunnel oxide layer is formed over a substrate, a peak floating gate layer of conducting material is formed over a portion of the tunnel oxide layer. An inter-gate insulating layer and a control gate layer are formed over the peak floating gate layer and then the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer are sequentially etched down to generate a control gate, an inter-gate insulating region, a peak floating gate and a tunnel oxide region. Finally, a source and a drain are defined adjoining the tunnel oxide region by using a self-align technique.

Abstract: The present invention relates to a method of fabricating a semiconductor device which reduces The leakage current by controlling an etch of a field oxide layer when a contact hole is formed. The present invention includes the steps of forming a in a semiconductor device is reduced. A field oxide layer defining an active area and a field area is formed on a semiconductor substrateof a first conductive type, forming a . A gate is formed on the an active area of the semiconductor substrate. by inserting a gate insulating layer between the semiconductor substrate and the gate, forming impurity regions of a second conductive type in the semiconductor are formed on the substrate in use of using the gate as a mask, forming a . A first insulating interlayer layer is formed on the semiconductor substrate by depositing an insulator of which having the heat expansion coefficient and lattice mismatch that are less than those of the semiconductor substrateto cover the field oxide layer and the gate, forming a .