Patents by Inventor Jagar Singh

Jagar Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9230913
    Abstract: Structures and methods to minimize parasitic capacitance in a circuit structure are provided. The structure may include a substrate supporting one or more circuits and one or more metallization layers above the substrate. The metallization layer includes a conductive pattern defined by an array of conductive fill elements, where the conductive fill elements of the array are discrete, electrically isolated elements sized to satisfy, at least in part, a pre-defined minimum area-occupation ratio for a chemical-mechanical polishing of the metallization layer, and to minimize parasitic capacitance within the metallization layer, as well as minimize parasitic capacitance between the metallization layer and the circuit, and if multiple metallization layers are present, between the layers.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: January 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Biswanath Senapati, Jagar Singh, Karthik Chandrasekaran
  • Publication number: 20150364426
    Abstract: Embodiments of the present invention provide an improved decoupling capacitor structure. A contact region is disposed over a source/drain region of the decoupling capacitor structure. Each contact region is formed as a plurality of segments, wherein an inter-segment gap separates a segment of the plurality of segments from an adjacent segment of the plurality of segments. Embodiments may include multiple contact regions between two gate regions. Arrays of decoupling capacitors may arranged as an alternating “checkerboard” pattern of P-well and N-well structures, and may be oriented at a diagonal angle to a metallization layer to facilitate connections of multiple decoupling capacitors within the array.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: Jagar Singh, Jerome Ciavatti, Anurag Mittal, Manfred Eller
  • Patent number: 9177951
    Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jagar Singh, Andy Wei, Mahadeva Iyer Natarajan
  • Publication number: 20150270400
    Abstract: Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).
    Type: Application
    Filed: March 18, 2014
    Publication date: September 24, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jagar Singh, Konstantin G. Korablev, Andy Chih-Hung Wei
  • Publication number: 20150263089
    Abstract: A non-planar diode is fabricated, with an n- or p-type raised structure, such as a fin, coupled to the substrate. A well of an opposite type is located under the raised structure, along with an area having additional impurity, located directly under the raised structure, and within the well. This additional implant creates a p-n junction within the substrate, the non-planar diode having an ideality factor in a range of 1 to about 1.05.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 17, 2015
    Inventors: Jagar SINGH, Andy WEI
  • Publication number: 20150255335
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an ILD layer of dielectric material overlying a semiconductor substrate that includes a device region to form first contact vias that expose active areas of the device region. The ILD layer is etched to form second contact vias that correspondingly expose a gate that is disposed in the device region and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region. The first contact vias and the second contact vias are filled with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 10, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Scott Beasor, Jagar Singh
  • Publication number: 20150236133
    Abstract: Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.
    Type: Application
    Filed: February 17, 2014
    Publication date: August 20, 2015
    Inventors: Jagar SINGH, Andy WEI, Gopal SRINIVASAN, Amaury GENDRON
  • Publication number: 20150228649
    Abstract: A fin of a FinFET, being p or n-type, includes a well encompassing the active region, the well being of the opposite type than the fin. An implant of the same type as the well is provided for the well tap at an edge of the active region. A dummy gate material on the fin between the source/drain and the well tap implant reduces an inherent resistance of a well tap contact.
    Type: Application
    Filed: February 10, 2014
    Publication date: August 13, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jagar Singh, Andy Wei
  • Publication number: 20150194419
    Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 9, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jagar Singh, Andy Wei, Mahadeva Iyer Natarajan
  • Publication number: 20150077086
    Abstract: A method for accurately electrically measuring a width of a fin of a FinFET, using a semiconductor fin quantum well structure is provided. The semiconductor fin quantum well structure includes a semiconductor substrate and at least one semiconductor fin coupled to the substrate. Each of the semiconductor fin is sandwiched by an electrical isolation layer from a top and a first side and a second side across from the first side, to create a semiconductor fin quantum well. At least one gate material is provided on each side of the electrical isolation layer. A dielectric layer is provided over the top of the electrical isolation layer to further increase the electrical isolation between the gate materials. The width of the semiconductor fin is measured accurately by applying a resonant bias voltage across the fin by applying voltage on the gate materials from either side. The peak tunneling current generated by the applied resonant bias voltage is used to measure width of the fin.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: GLOBALFOUNDRIES Inc
    Inventor: Jagar Singh
  • Publication number: 20150035053
    Abstract: Semiconductor devices and methods for manufacturing an LDMOS FinFET integrated circuit. The intermediate semiconductor device includes a substrate, a first well in the substrate, a second well in the substrate, and at least two polysilicon gates. The first well overlaps the second well and the at least one first gate is disposed over the first well and at least one second gate is disposed over the second well. The method includes forming a channel region and a drift region in the substrate, wherein the channel region overlaps the drift region, forming a shallow trench isolation region in the drift region, forming at least one first gate over the channel region, forming at least one second gate over the shallow trench isolation region, and applying at least one metal layer over the at least one first gate and the at least one second gate.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Jagar SINGH
  • Patent number: 8946039
    Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jagar Singh, Shesh Mani Pandey, Roderick Miller, Nam Sung Kim
  • Publication number: 20150001630
    Abstract: A semiconductor FinFET device in fabrication includes a semiconductor substrate and at least one semiconductor fin coupled to the substrate. Each of the semiconductor fins further include a single drain branch coupled to at least two source branches at a common area, with the two source branches acting together as a source. A channel area is situated in the common area. In one example, the single drain branch and two source branches are coupled at the common area to form a generally Y-shaped fin. Further fabrication to complete the FinFET may then proceed.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventor: Jagar Singh
  • Publication number: 20140231960
    Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).
    Type: Application
    Filed: February 15, 2013
    Publication date: August 21, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Nam Sung Kim, Roderick M. Miller, Shesh M. Pandey, Jagar Singh
  • Patent number: 8476684
    Abstract: Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: July 2, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Edward John Coyne, Paul Malachy Daly, Jagar Singh, Seamus Whiston, Patrick Martin McGuinness, William Allan Lane
  • Publication number: 20120074493
    Abstract: Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventors: Edward John Coyne, Paul Malachy Daly, Jagar Singh, Seamus Whiston, Patrick Martin McGuinness, William Allan Lane
  • Publication number: 20090179281
    Abstract: An N-type Schottky barrier Source/Drain Transistor (N-SSDT) that uses ytterbium silicide (YbSi2-x) for the source and drain is described. The structure includes a suitable capping layer stack.
    Type: Application
    Filed: February 4, 2009
    Publication date: July 16, 2009
    Inventors: Shiyang Zhu, Jingde Chen, Sungjoo Lee, Ming Fu Li, Jagar Singh, Chungxiang Zhu, Dim-Lee Kwong
  • Publication number: 20090163005
    Abstract: A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 25, 2009
    Inventors: Shiyang Zhu, Jingde Chen, Sungjoo Lee, Ming Fu Li, Jagar Singh, Chunxiang Zhu, Dim-Lee Kwong
  • Patent number: 7504328
    Abstract: A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: March 17, 2009
    Assignee: National University of Singapore
    Inventors: Shiyang Zhu, Jingde Chen, Sungjoo Lee, Ming Fu Li, Jagar Singh, Chunxiang Zhu, Dim-Lee Kwong
  • Patent number: 7002175
    Abstract: A double barrier resonant tunneling diode (RTD) is formed and integrated with a level of CMOS/BJT/SiGe devices and circuits through processes such as metal-to-metal thermocompressional bonding, anodic bonding, eutectic bonding, plasma bonding, silicon-to-silicon bonding, silicon dioxide bonding, silicon nitride bonding and polymer bonding or plasma bonding. The electrical connections are made using conducting interconnects aligned during the bonding process. The resulting circuitry has a three-dimensional architecture. The tunneling barrier layers of the RTD are formed of high-K dielectric materials such as SiO2, Si3N4, Al2O3, Y2O3, Ta2O5, TiO2, HfO2, Pr2O3, ZrO2, or their alloys and laminates, having higher band-gaps than the material forming the quantum well, which includes Si, Ge or SiGe. The inherently fast operational speed of the RTD, combined with the 3-D integrated architecture that reduces interconnect delays, will produce ultra-fast circuits with low noise characteristics.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: February 21, 2006
    Assignee: Agency for Science, Technology and Research
    Inventors: Jagar Singh, Yong Tian Hou, Ming Fu Li