Patents by Inventor Jagar Singh

Jagar Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160181393
    Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.
    Type: Application
    Filed: March 1, 2016
    Publication date: June 23, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Jagar SINGH
  • Patent number: 9349718
    Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Andy Wei, Mahadeva Iyer Natarajan, Manjunatha Prabhu, Anil Kumar
  • Patent number: 9343456
    Abstract: A method of forming a metal gate diode ESD protection device and the resulting device are provided. Embodiments include forming a metal gate diode including a metal gate on a substrate; forming an n-type cathode on a first side of the metal gate diode; and forming a p-type anode on a second side of the metal gate diode, opposite the first side.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: May 17, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Amaury Gendron-Hansen, Jagar Singh, Andy Wei
  • Publication number: 20160126239
    Abstract: Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 5, 2016
    Inventors: Jagar Singh, Sanford Chu
  • Patent number: 9330971
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an ILD layer of dielectric material overlying a semiconductor substrate that includes a device region to form first contact vias that expose active areas of the device region. The ILD layer is etched to form second contact vias that correspondingly expose a gate that is disposed in the device region and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region. The first contact vias and the second contact vias are filled with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: May 3, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Scott Beasor, Jagar Singh
  • Publication number: 20160118414
    Abstract: Co-fabrication of a radio-frequency (RF) semiconductor device with a three-dimensional semiconductor device includes providing a starting three-dimensional semiconductor structure, the starting structure including a bulk silicon semiconductor substrate, raised semiconductor structure(s) coupled to the substrate and surrounded by a layer of isolation material. Span(s) of the layer of isolation material between adjacent raised structures are recessed, and a layer of epitaxial semiconductor material is created over the recessed span(s) of isolation material over which another layer of isolation material is created. The RF device(s) are fabricated on the layer of isolation material above the epitaxial material, which creates a local silicon-on-insulator, while the three-dimensional semiconductor device(s) can be fabricated on the raised structure(s).
    Type: Application
    Filed: October 28, 2014
    Publication date: April 28, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jagar SINGH, Srikanth Balaji SAMAVEDAM
  • Publication number: 20160118473
    Abstract: A non-planar Schottky diode includes a semiconductor substrate of a first type, the first type including one of n-type and p-type. The structure further includes raised semiconductor structure(s) of a second type opposite the first type coupled to the substrate, isolation material surrounding a lower portion of the raised structure(s), a first well of the second type directly under the raised structure(s), a guard ring of the first type around an edge of a top portion of the first well, a conformal layer of silicide over a top portion of the raised structure(s) above the isolation material, and a common contact above the conformal layer of silicide. The non-planar Schottky diode can be fabricated with non-planar transistors, e.g., FinFETs.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 28, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jagar SINGH, Jerome CIAVATTI
  • Patent number: 9324827
    Abstract: A non-planar Schottky diode includes a semiconductor substrate of a first type, the first type including one of n-type and p-type. The structure further includes raised semiconductor structure(s) of a second type opposite the first type coupled to the substrate, isolation material surrounding a lower portion of the raised structure(s), a first well of the second type directly under the raised structure(s), a guard ring of the first type around an edge of a top portion of the first well, a conformal layer of silicide over a top portion of the raised structure(s) above the isolation material, and a common contact above the conformal layer of silicide. The non-planar Schottky diode can be fabricated with non-planar transistors, e.g., FinFETs.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Jerome Ciavatti
  • Publication number: 20160111422
    Abstract: Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins.
    Type: Application
    Filed: December 10, 2015
    Publication date: April 21, 2016
    Inventor: Jagar SINGH
  • Patent number: 9312371
    Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: April 12, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jagar Singh
  • Publication number: 20160071962
    Abstract: A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Biswanath SENAPATI, Jagar SINGH
  • Publication number: 20160071835
    Abstract: A method of forming a metal gate diode ESD protection device and the resulting device are provided. Embodiments include forming a metal gate diode including a metal gate on a substrate; forming an n-type cathode on a first side of the metal gate diode; and forming a p-type anode on a second side of the metal gate diode, opposite the first side.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Inventors: Amaury GENDRON-HANSEN, Jagar SINGH, Andy WEI
  • Publication number: 20160064372
    Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 3, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jagar SINGH, Andy WEI, Mahadeva Iyer NATARAJAN, Manjunatha PRABHU, Anil KUMAR
  • Publication number: 20160064371
    Abstract: Protecting non-planar output transistors from electrostatic discharge (ESD) events includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate with a well of n-type or p-type. The provided non-planar structure further includes raised semiconductor structure(s) coupled to the substrate, non-planar transistor(s) of a type opposite the well, each transistor being situated on one of the raised structure(s), the non-planar transistor(s) each including a source, a drain and a gate, the non-planar structure further including parasitic bipolar junction transistor(s) (BJT(s)) on the raised structure(s), each BJT including a collector and an emitter situated on the raised structure and a base being the well, and a well contact for the base of the BJT.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jian-Hsing LEE, Jagar SINGH, Manjunatha PRABHU, Anil KUMAR, Mahadeva Iyer NATARAJAN, Min-hwa CHI
  • Patent number: 9276088
    Abstract: Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jagar Singh
  • Publication number: 20160056231
    Abstract: Semiconductor devices and fabrication methods thereof are provided. The semiconductor devices include: a substrate, the substrate including a p-type well adjoining an n-type well; a first p-type region and a first n-type region disposed within the n-type well of the substrate, where the first p-type region at least partially encircles the first n-type region; and a second p-type region and a second n-type region disposed in the p-type well of the substrate, where the second n-type region at least partially encircles the second p-type region. In one embodiment, the first p-type region fully encircles the first n-type region and the second n-type region fully encircles the second p-type region. In another embodiment, the semiconductor device may be a bipolar junction transistor or a rectifier.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 25, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Jagar SINGH
  • Patent number: 9263385
    Abstract: Semiconductor fuses with epitaxial fuse link regions and fabrication methods thereof are presented. The methods include: fabricating a semiconductor fuse including an anode region and a cathode region electrically linked by a fuse link region, and the fabricating including: forming, epitaxially, the fuse link region between the anode region and the cathode region, wherein the fuse link region facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region thereof. The semiconductor fuses include: an anode region and a cathode region electrically linked by a fuse link region, wherein the fuse link region includes an epitaxial structure and facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region, wherein the epitaxial structure is in at least partial crystallographic alignment with the anode region and the cathode region of the semiconductor fuse.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jagar Singh, Anurag Mittal
  • Publication number: 20160027905
    Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.
    Type: Application
    Filed: July 24, 2014
    Publication date: January 28, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Jagar SINGH
  • Publication number: 20160020204
    Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.
    Type: Application
    Filed: September 30, 2015
    Publication date: January 21, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jagar SINGH, Andy WEI, Mahadeva Iyer NATARAJAN
  • Publication number: 20160020277
    Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.
    Type: Application
    Filed: September 30, 2015
    Publication date: January 21, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jagar SINGH, Andy WEI, Mahadeva Iyer NATARAJAN