Patents by Inventor Jagar Singh

Jagar Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10115719
    Abstract: Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 30, 2018
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Jagar Singh, Sanford Chu
  • Patent number: 10056368
    Abstract: A diode includes a plurality of fins defined in a semiconductor substrate. An anode region is defined by a doped region in a first surface portion of each of the plurality of fins and in a second surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins. The doped region includes a first dopant having a first conductivity type and is contiguous between the adjacent fins. A cathode region is defined by an inner portion of each of the plurality of fins positioned below and contacting the first surface portion and a third portion of the semiconductor substrate positioned below and contacting the second surface portion. The cathode region is contiguous and the dopants in the cathode region and anode region have opposite conductivity types. A junction is defined between the anode region and the cathode region. A first contact interfaces with the anode region.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kasun Anupama Punchihewa, Jagar Singh
  • Patent number: 10020386
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage, analog bipolar devices and methods of manufacture. The structure includes: a base region formed in a substrate; a collector region formed in the substrate and comprising a deep n-well region and an n-well region; and an emitter region formed in the substrate and comprising a deep n-well region and an n-well region.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Baofu Zhu
  • Publication number: 20180175179
    Abstract: A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric.
    Type: Application
    Filed: February 15, 2018
    Publication date: June 21, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Biswanath SENAPATI, Jagar SINGH
  • Patent number: 9966459
    Abstract: A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: May 8, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Biswanath Senapati, Jagar Singh
  • Patent number: 9960248
    Abstract: Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jagar Singh
  • Publication number: 20180108732
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 19, 2018
    Inventors: Jiehui Shu, Baofu Zhu, Haifeng Sheng, Jinping Liu, Shesh Mani Pandey, Jagar Singh
  • Patent number: 9905668
    Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: February 27, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jagar Singh
  • Publication number: 20180026113
    Abstract: Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region.
    Type: Application
    Filed: June 7, 2017
    Publication date: January 25, 2018
    Inventor: Jagar SINGH
  • Patent number: 9876010
    Abstract: A semiconductor structure includes a substrate. A gate structure is disposed over the substrate. The gate structure includes: a pair of gate spacers extending generally vertically from the substrate, gate metal disposed between the spacers, and a self-aligned contact (SAC) cap disposed over the gate metal to form a top of the gate structure. A resistor is disposed directly upon the SAC cap such that no additional layer is disposed between the resistor and SAC cap. The resistor is composed of a material suitable to provide a predetermined resistance to a current to be conducted therethrough. A pair of resistor contacts are electrically connected to the resistor and spaced to provide the predetermined resistance to the current.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Jagar Singh, Jerome Ciavatti
  • Publication number: 20180006019
    Abstract: A diode includes a plurality of fins defined in a semiconductor substrate. An anode region is defined by a doped region in a first surface portion of each of the plurality of fins and in a second surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins. The doped region includes a first dopant having a first conductivity type and is contiguous between the adjacent fins. A cathode region is defined by an inner portion of each of the plurality of fins positioned below and contacting the first surface portion and a third portion of the semiconductor substrate positioned below and contacting the second surface portion. The cathode region is contiguous and the dopants in the cathode region and anode region have opposite conductivity types. A junction is defined between the anode region and the cathode region. A first contact interfaces with the anode region.
    Type: Application
    Filed: August 25, 2017
    Publication date: January 4, 2018
    Inventors: Kasun Anupama Punchihewa, Jagar Singh
  • Publication number: 20170338180
    Abstract: A method for producing semiconductor devices including an electrical fuse (e-fuse) and the resulting device are provided. Embodiments include forming a gate electrode (PC); forming at least one gate contact (CB) over the PC; forming at least one source/drain contact (CA); and forming an e-fuse including a resistor metal (RM) between at least one CB and an equal number of CAs to dissipate heat generated by the PC.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 23, 2017
    Inventors: Scott BEASOR, Jagar SINGH
  • Publication number: 20170317071
    Abstract: A method incudes forming a first plurality of fins having a first width in a first region of a semiconductor substrate. A second plurality of fins having a second width greater than the first width is formed in a second region of a semiconductor substrate. A doped region is formed in a surface portion of the second plurality of fins to define an anode region of a diode. A junction is defined between the doped region and a cathode region of the second plurality of fins. A first contact interfacing with the anode region is formed.
    Type: Application
    Filed: April 27, 2016
    Publication date: November 2, 2017
    Inventors: Kasun Anupama Punchihewa, Jagar Singh
  • Patent number: 9793262
    Abstract: A method includes forming a first plurality of fins having a first width in a first region of a semiconductor substrate. A second plurality of fins having a second width greater than the first width is formed in a second region of a semiconductor substrate. A doped region is formed in a surface portion of the second plurality of fins to define an anode region of a diode. A junction is defined between the doped region and a cathode region of the second plurality of fins. A first contact interfacing with the anode region is formed.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kasun Anupama Punchihewa, Jagar Singh
  • Patent number: 9780212
    Abstract: A method for accurately electrically measuring a width of a fin of a FinFET, using a semiconductor fin quantum well structure is provided. The semiconductor fin quantum well structure includes a semiconductor substrate and at least one semiconductor fin coupled to the substrate. Each of the semiconductor fin is sandwiched by an electrical isolation layer from a top and a first side and a second side across from the first side, to create a semiconductor fin quantum well. At least one gate material is provided on each side of the electrical isolation layer. A dielectric layer is provided over the top of the electrical isolation layer to further increase the electrical isolation between the gate materials. The width of the semiconductor fin is measured accurately by applying a resonant bias voltage across the fin by applying voltage on the gate materials from either side. The peak tunneling current generated by the applied resonant bias voltage is used to measure width of the fin.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jagar Singh
  • Patent number: 9773781
    Abstract: A semiconductor structure includes a substrate. A gate structure is disposed over the substrate. The gate structure includes: a pair of gate spacers extending generally vertically from the substrate, gate metal disposed between the spacers, and a self-aligned contact (SAC) cap disposed over the gate metal to form a top of the gate structure. A first capacitor plate is disposed directly upon the SAC cap such that no additional layer is disposed between the resistor and SAC cap. An insulator layer and a second capacitor plate are disposed on the first capacitor plate forming a MIM capacitor. A pair of capacitor plate contacts are electrically connected to the first capacitor plate and the second capacitor plate.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: September 26, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Jagar Singh, Jerome Ciavatti
  • Patent number: 9741713
    Abstract: A semiconductor structure includes a semiconductor substrate of n-type or p-type, a well of a type opposite the substrate, the well acting as the base of a diode, a first region of the same type as the substrate at a top of the well, a second region of the same type as the substrate is situated separate from the first region at the top of the well, the first region acting as an emitter of the diode and the second region acting as a collector of the diode, and a gate situated between the first region and second region over a top surface of the well.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jagar Singh
  • Patent number: 9704966
    Abstract: Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jagar Singh
  • Publication number: 20170162647
    Abstract: An illustrative method includes, among other things, forming a plurality of fins. A subset of the plurality of fins is selectively removed, leaving at least a first fin to define a first fin portion and at least a second fin to define a second fin portion. A first type of dopant is implanted into a substrate to define a resistor body and the first type of dopant is implanted into the first and second fins. The first fin portion is disposed above a first end of the resistor body and the second fin is disposed above a second end of the resistor body. An insulating layer is formed above the resistor body. At least one gate structure is formed above the insulating layer and above the resistor body.
    Type: Application
    Filed: February 20, 2017
    Publication date: June 8, 2017
    Inventor: Jagar Singh
  • Patent number: 9666717
    Abstract: Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 30, 2017
    Assignee: GLOBAL FOUNDRIES, INC.
    Inventors: Jagar Singh, Konstantin G. Korablev, Andy Chih-Hung Wei