Patents by Inventor James A. Cunningham

James A. Cunningham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110260088
    Abstract: A valve includes a valve ball and a complex metal valve seat having a groove for receiving a low pressure seal and a convex ridge on each side of the groove. The valve ball contacts only the low pressure seal at relatively low pressures and contacts the convex ridges at relatively higher pressures to provide a metal-to-metal seal. Typically, the low pressure seal is an O-ring and the volume provided by the groove and its transition to the convex ridges is sufficient to accommodate the volume of the O-ring when the valve ball contacts the convex ridges.
    Type: Application
    Filed: April 21, 2010
    Publication date: October 27, 2011
    Inventor: James A. Cunningham
  • Patent number: 7879360
    Abstract: The present invention is directed to nanoparticulate active agent compositions comprising at least one peptide as a surface stabilizer. Also encompassed by the invention are pharmaceutical compositions comprising a nanoparticulate active agent composition of the invention and methods of making and using such nanoparticulate and pharmaceutical compositions.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: February 1, 2011
    Assignee: Elan Pharma International, Ltd.
    Inventors: James Cunningham, Elaine Merisko Liversidge
  • Publication number: 20100232875
    Abstract: A mechanical coupling for transferring torque from a first component that rotates about an axis to a second component that also rotates about the axis is provided. The coupling allows different rates of expansion of the first and second components in the radial direction by permitting sliding in the radial direction of the components relative to one another. The coupling comprises first and second circular arrays of teeth formed on the first component and second component, respectively, and centered on the axis. The first circular array of teeth are intermeshed with the second circular array of teeth, wherein rotation of the first component causes first mating sides on the first circular array of teeth to bear against second mating sides on the second circular array of teeth transferring torque to the second component. The first and second mating sides extend both axially and radially and are essentially curved.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 16, 2010
    Inventors: James Cunningham, Adrian Theodorus Sanders, AC Mackenzie, Andrew Shepherd
  • Publication number: 20100224996
    Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.
    Type: Application
    Filed: May 18, 2010
    Publication date: September 9, 2010
    Inventor: James A. Cunningham
  • Publication number: 20090321938
    Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.
    Type: Application
    Filed: September 4, 2009
    Publication date: December 31, 2009
    Applicant: BECK SEMICONDUCTOR LLC
    Inventor: James A. Cunningham
  • Patent number: 7609972
    Abstract: A technique for acquiring and tracking terminals in a free-space laser communication system involves exchanging beacon laser beams between the terminals to acquire and then track the terminals such that data laser beams exchanged by the terminals for communication are steered based on feedback from detection of the beacon laser beams. The beacon laser beams used for acquisition have a greater beam divergence than those used for tracking. Gimbals provide coarse steering of the data laser beams, and steering mirrors provide fine steering. GPS position data exchanged via an RF link can be used for initial pointing of the beacon laser beams for acquisition. The beacon laser beams can be chopped such that all terminals can use the same beacon wavelength and are distinguished by using different chopping frequencies. By detecting a chopped signal, the position sensor detector can be AC coupled to reduce sensitivity to solar radiation and glint.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: October 27, 2009
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventors: James Cunningham, Dean Grinch, Donald Fisher
  • Patent number: 7585766
    Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: September 8, 2009
    Inventor: James A. Cunningham
  • Publication number: 20090064329
    Abstract: The zero-hour quarantine comprises a tool for flagging potentially harmful messages/files prior to having an anti-virus signature published for a particular virus. The suspect file is sent to the zero-hour quarantine and periodically scanned, giving time for creation of a signature file that would then detect the virus. An example method may include receiving and examining a message for attributes indicative of its undesirability, and assigning a threat score to the message. The method may comprise disposing of the message by comparing the threat score to first and second thresholds, and the message sent to a permanent quarantine if the threat score passes the first threshold. The message is sent to the zero-hour quarantine if the assigned threat score does not pass the second threshold but passes the second threshold, or is delivered to the recipient if the assigned threat score does not pass the first or second threshold.
    Type: Application
    Filed: June 25, 2008
    Publication date: March 5, 2009
    Applicant: GOOGLE INC.
    Inventors: Kenneth K. Okumura, Adam S. Dawes, Peter K. Lund, Erik S. Chen, Dmitriy Y. Larin, Carl S. Gutekunst, James Cunningham, Scott M. Petry
  • Publication number: 20090053263
    Abstract: The present invention relates to treatment of infection by enveloped viruses through the use of papain-like cysteine protease inhibitors and kits thereof. Specifically, methods for treatment of filoviruses as well as other enveloped viruses such as Nipah, in particular using cathepsin inhibitors are described.
    Type: Application
    Filed: February 23, 2006
    Publication date: February 26, 2009
    Applicant: The Brigham and Women's Hospital, Inc.
    Inventors: James Cunningham, Kartik Chandran
  • Patent number: 7426796
    Abstract: A control system for controlling the release of an accessory from any quick hitch coupler coupling the accessory to a hydraulically operable arm of a machine, operated by a pressurized hydraulic system. The control system can be used with a coupler for coupling an accessory to a dipper arm and a control system for such a coupler, such as a quick hitch coupler for coupling an accessory to a dipper arm of a back actor such as may be used by an earth working apparatus. The quick hitch coupler comprises a body member adapted for coupling to the dipper arm, a fixed engaging means mounted on the body member for engaging a first one of a pair of coupling pins mounted on the accessory, and a moveable engaging means mounted on the body member for engaging a second one of the pair of coupling pins of the accessory.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: September 23, 2008
    Assignee: Geith Patents Limited
    Inventors: Bartholomew James Cunningham, James David Barron, Anthony McKeown
  • Publication number: 20080176395
    Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.
    Type: Application
    Filed: March 26, 2008
    Publication date: July 24, 2008
    Applicant: Beck Semiconductor LLC
    Inventor: James A. Cunningham
  • Patent number: 7385982
    Abstract: Systems and methods for providing fractional bandwidth communication channels in classes of service that do not normally support these types of channels. In one embodiment, a method comprises receiving one or more frames, wherein each frame contains non-QoS header information, classifying the one or more frames based on the corresponding non-QoS header information and scheduling delivery of the one or more frames based upon corresponding frame classifications, wherein frames in classifications corresponding to QoS circuits are scheduled in a manner that meets QoS requirements associated with the QoS circuits. When the frames are classified, they are forwarded to dynamically allocated queues corresponding to the respective classifications. Frames are scheduled for delivery from the queues according to a modified bin-filling algorithm that is designed to meet the QoS requirements of the respective circuits. This method may be implemented, for example, in a Fibre Channel Class 2 or Class 3 fabric.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: June 10, 2008
    Assignee: Next Generation Systems, Inc.
    Inventors: Gary G. Warden, James A. Cunningham, Nathan A. Kragick
  • Patent number: 7372152
    Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: May 13, 2008
    Assignee: Beck Semiconductor LLC
    Inventor: James A. Cunningham
  • Patent number: 7361589
    Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 22, 2008
    Assignee: Beck Semiconductor LLC
    Inventor: James A. Cunningham
  • Patent number: 7351655
    Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 1, 2008
    Assignee: Beck Semiconductor LLC
    Inventor: James A. Cunningham
  • Publication number: 20070269271
    Abstract: Whereas pull lines are utilized for installing electric wires in electrical conduit between junction boxes by attaching a pull line to the open end of a high-speed line carrier closed by an elastomer molded bulb of specific dimensions relative to the type and size of conduit and in which the hollow core device is slightly smaller in diameter than the conduit through which it travels, said combination of hollow core and molded bulb fashioned to complementary conduit creating physical characteristics, including a frictionless seal, allowing same to travel through conduit at high speeds, measurable in feet per second with little resistance, in response to a vacuum created at opposing end of conduit, or in response to a driving force of air applied at insertion point of same, or in response to a combination of these means. Additionally, usage on larger scale applies to waste disposal networks with same results.
    Type: Application
    Filed: May 14, 2007
    Publication date: November 22, 2007
    Inventors: William Smith, James Cunningham
  • Patent number: D602155
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: October 13, 2009
    Assignee: Animas Corporation
    Inventors: Nick Foley, James Cunningham Glencross, James Harkness
  • Patent number: D602586
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: October 20, 2009
    Assignee: Animas Corporation
    Inventors: Nick Foley, James Cunningham Glencross, James Harkness, Martin Crofton, Peter Krulevitch
  • Patent number: D615393
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: May 11, 2010
    Assignee: Specialty Electrical, LLC
    Inventors: Phillip James Cunningham, Jr., Scotty Ray Gross
  • Patent number: RE41538
    Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: August 17, 2010
    Inventor: James A. Cunningham