Abstract: Some examples described herein provide for a shield in an integrated circuit (IC) structure for memory protection. In an example, an IC structure includes a semiconductor material, an interconnect structure, and a shield. The semiconductor material has a protected region. Devices are disposed in a first side of the semiconductor material in the protected region. The interconnect structure is disposed on the first side of the semiconductor material. The interconnect structure interconnects the devices in the protected region. The shield is disposed on a second side of the semiconductor material opposite from the first side of the semiconductor material. The shield is positioned aligned with the protected region.

Abstract: Examples described herein generally relate to devices that include electrostatic discharge (ESD) protection in a chip stack. In an example, a device includes a chip stack including first and second chips, ground and power supply voltage nodes, and first and second resistor-capacitor (RC) clamps. The second chip is disposed on and attached to the first chip. The ground and power supply voltage nodes are connected between and extend in the first and second chips, and are connected to the ground and power supply voltage exterior connector pads, respectively, of the first chip. The first and second RC clamps are disposed in the first and second chips, respectively. The first and second RC clamps are connected to and between the ground node and the power supply voltage node. An RC-time constant of the second RC clamp is less than an RC-time constant of the first RC clamp.

Abstract: Examples described herein provide a circuit and methods for self-testing to detect damage to a device, which damage may be caused by an Electro-Static Discharge (ESD) event. In an example, an integrated circuit includes an input/output circuit, an ESD protection circuit, and a system monitor. The input/output circuit has an input/output node. The ESD protection circuit is connected to the input/output node. The system monitor has a driving/measurement node selectively connectable to the input/output node. The system monitor is configured to drive and measure a voltage of the driving/measurement node. The system monitor is further configured to determine, based on driving and measuring the voltage of the driving/measurement node, whether a damaged device is present. The damaged device is in the input/output circuit or the ESD protection circuit.

Abstract: Disclosed herein are integrated circuit devices and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad is configured to connect to a second supply voltage or ground. A first charge-sensitive circuitry formed in the first body is coupled between the first and second contact pads. A first RC clamp formed in the first body is coupled between the first and second contact pads. The first RC clamp includes at least two BigFETs coupled between the first and second contact pads, and a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs.

Abstract: Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

Abstract: An electronics-harmful-radiation (EHR) monitoring system includes an EHR measurement circuit. The EHR measurement circuit includes a first device, a single event upset (SEU) detector circuit configured to determine a first number of SEUs of the first device during a first period, and an EHR measurement generator configured to generate a first EHR value based on the first number of SEUs and the first period.

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

Abstract: Disclosed herein are integrated circuit devices and and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad is configured to connect to a second supply voltage or ground. A first charge-sensitive circuitry formed in the first body is coupled between the first and second contact pads. A first RC clamp formed in the first body is coupled between the first and second contact pads. The first RC clamp includes at least two BigFETs coupled between the first and second contact pads, and a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs.

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

Abstract: FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the fin and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second isolation layer has a thickness greater than a thickness of the first isolation layer.

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

Abstract: An integrated circuit device is described. The integrated circuit device comprises a substrate having transmitter for receiving a signal to be transmitted to a receiver of the substrate by way of a transmission channel; a first plurality of contacts adapted to receive a first integrated circuit die, wherein a contact of the first plurality of contacts is adapted to receive the signal to be transmitted by the transmitter; a second plurality of contacts adapted to receive a second integrated circuit die, wherein a contact of the second plurality of contacts is adapted to receive the signal transmitted by the transmitter and received by the receiver; a first resistive element coupled between a contact of the first plurality of contacts and the transmitter; and a second resistive element coupled between a contact of the second plurality of contacts and the receiver. A method of transmitting data in an integrated circuit is also described.

Abstract: An example integrated circuit (IC) assembly includes: a substrate, and a first IC die stacked on a second IC die, a stack of the first IC die and the second IC die mounted to the substrate. The first IC die includes an active side, a backside, a plurality of through-silicon vias (TSVs) exposed on the backside, an electrostatic discharge (ESD) circuit on the active side, and metallization on the active side. The metallization includes a first plurality of metal layers disposed on the active side and a second plurality of metal layers disposed on the first plurality of metal layers, each of the second plurality of metal layers thicker than each of the first plurality of metal layers. The metallization further includes a U-route that electrically couples a first TSV of the plurality of TSVs to the ESD circuit, the U-route including a conductive path through the second plurality of metal layers.

Abstract: FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET transistor is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the in and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second oxide isolation layer has a thickness greater than a thickness of the first isolation layer.

Abstract: A circuit for implementing a discharge path in an input/output circuit of an integrated circuit is described. The circuit comprises an input/output pad; a first node coupled to a power reference voltage; a first impedance element implemented between the first node and the input/output pad; a second node coupled to a ground reference voltage; and a second impedance element implemented between the second node and the input/output pad. A method of implementing a discharge path in an input/output circuit of an integrated circuit is also disclosed.

Abstract: Methods and apparatus are described for detecting both single event latch-up (SEL) and electrical overvoltage stress (EOS) using a single, reconfigurable detection circuit. One example circuit capable of detecting a latch-up state and an overvoltage condition generally includes an impedance element coupled to a power supply node; a voltage divider coupled to the power supply node; a multiplexer having a first input coupled to a tap of the voltage divider, a second input coupled to a first portion of the impedance element, and a third input coupled to a second portion of the impedance element; a reference generator; and an analog-to-digital converter (ADC) having a first input coupled to an output of the multiplexer and a second input coupled to an output of the reference generator.

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors for coupling an integrated circuit die to the interposer to provide a stacked die. The interposer includes a pad coupled to a conductive network of the interposer to dissipate electrostatic charge from the interposer.

Abstract: A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.

Abstract: Embodiments herein describe techniques for wafer to wafer stacking of integrated circuit chips (e.g., dice) to form stacked IC devices. In one example, a stacked IC device is provided that includes a first wafer, a second wafer, and first conductive bridge. The second wafer is stacked on and secured to the first wafer. The second wafer has a plurality of IC dice that are communicatively coupled to a plurality of IC dice formed on the first wafer. The first conductive bridge has a first end that is sandwiched between the first and second wafers. The first conductive bridge shorts exposed pads of dice formed in the exclusion zones of the first and second wafers.