Abstract: A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.

Abstract: A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.

Abstract: A method, system, and apparatus for re-conveying input/output (I/O) operations utilizing a sequential-access data storage device secondary communication port are disclosed. In accordance with one embodiment, a method is provided which comprises receiving an input/output (I/O) operation request via a first communication port of a primary data storage device, processing the I/O operation request utilizing the primary data storage device, and re-conveying the I/O operation request to a secondary data storage device substantially simultaneously with the processing via a second communication port of the primary data storage device. In the described embodiment, the primary data storage device comprises a sequential-access data storage device.

Abstract: A method, system, and a device have a data storage drive for an automated data storage library in which a data storage drive may have in one embodiment, both a host-drive interface port and a host-library interface port. In one aspect, drive commands from a host system are conducted primarily through the host-drive interface port and a host-drive interface path to a drive controller of the data storage drive. In addition, library commands from the host system to a library controller may be conducted primarily through the host-library interface port and a host-library interface path to a library communication port of the data storage drive. In one embodiment, the drive commands from a host system are conducted primarily through the host-drive interface port and the host-drive interface path to a drive controller of the data storage drive.

Abstract: Provided are a method, system, and article of manufacture for writing data in a tape medium having wraps. A layout of the tape is provided including at least one segment within a full length of first set of wraps for writing user data and at least one segment within a full length of a second set of wraps for writing a work copy of the user data. User data is received to write to the tape medium. Detection is made of whether data writing is occurring in a specified write mode. A work copy is written to available segments in the second set of wraps not having user data in response to the data writing occurring in the specified write mode.

Abstract: A method is disclosed to transfer information between data storage devices. The method provides an information storage assembly comprising a frame, a memory device disposed on that frame, information written to that memory device, a power supply removeably attached to the frame, and a first data storage device comprising a first identity removeably attached the frame. If the method detects an error in the first data storage device, then the method removes the first data storage device from the frame. The method further provides a replacement data storage device, removeably attaches that replacement data storage device to the frame, and determines if the replacement device uses the first configuration information. If the replacement device uses the first configuration information, then the method provides the first configuration information to the replacement data storage device from the memory device.

Abstract: Provided are a method, system, and program for writing data in a tape medium having wraps. A layout of the tape is provided including at least one segment within a full available length of a first set of wraps for writing user data and at least one segment within a full length of a second set of wraps for writing a work copy of the user data. User data is received to write to the tape medium and detecting is performed as to whether the data being written is occurring in a specified write mode. If the data writing is not occurring in the specified write mode, then writing the received user data to one segment in the first set of wraps. If the data writing is occurring in the specified write mode, then writing a work copy to available full length wraps not having user data.

Abstract: A system, a method, and article of manufacture are employed to clean the input/output transducers on tape drives, verified by the tape drives reading alphanumeric information from data tracks and servo tracks of a cleaner tape. An aggressive cleaning frontcoat section of the cleaner tape can be used to provide additional cleaning action, and the cleanliness of the data read elements, data write elements, and the servo heads. A less-abrasive cleaning section may be used to clean less difficult types of contaminants. In this manner, the cleanliness of the data read elements, the data write elements, and the servo heads can be verified. A cleaning section may also be used as a leader section of a self-characterization section. Alternatively, a magnetic data tape section may be included for self-characterization.

Abstract: An electrically programmable fuse includes a metal-oxide-semiconductor (MOS) programmable transistor that is gate-source coupled by a resistive element. The resistive element can comprise a gate-source coupled MOS transistor. If the MOS transistor is unprogrammed, then the resistive element ensures that the programmable transistor is turned off during read operations. However, when a programming voltage is applied across the source and drain terminals of the programmable transistor, the resistive element allows the programming voltage to be capacitively coupled to the gate of the programmable transistor from its drain. This turns the programmable transistor on, thereby reducing the snapback voltage of the programmable transistor, and hence, the required programming voltage. Once the snapback mode is entered, current flow through the programmable transistor increases until thermal breakdown occurs and the programmable transistor shorts out.

Abstract: Synchronized data is written to magnetic tape while reducing the number of backhitches. A controller detects a pattern of synchronizing events for received data records to be written to tape; writes each transaction of data records to the magnetic; tape; accumulates the synchronized transactions in a buffer; and subsequently recursively writes the accumulated transactions of data records from the buffer to the magnetic tape in a sequence. A single backhitch may be employed to place the recursively written accumulated data records following the preceding data, maximizing performance and capacity.

Abstract: A method to transfer information between data storage devices. The method provides an information storage assembly comprising a frame, a memory device disposed on that frame, information written to that memory device, a power supply removeably attached to the frame, and a first data storage device comprising a first identity removeably attached the frame. The method writes first configuration information to the memory device. If the method detects an error in the first data storage device, then the method removes the first data storage device from the frame. The method further provides a replacement data storage device, removeably attaches that replacement data storage device to the frame, and determines if the replacement device uses the first configuration information. If the replacement device uses the first configuration information, then the method provides the first configuration information to the replacement data storage device from the memory device.

Abstract: An electrical connection of a transfer station releasably, repeatably electrically couples with respect to a matching connection of a portable cartridge. A substrate in the portable cartridge has electrical contacts on a facing surface. In the transfer station, a matching circuitized flexible substrate has electrical contacts on a facing surface thereof, which are arranged to match the portable cartridge electrical contacts when in a face-to-face relationship. An elastomeric compression element, at the rear of the matching substrate, has individual protruding compression members contacting the rear surface and registered with corresponding individual electrical contacts. Elongated electrical contacts are registered with two adjacent individual compression members.

Abstract: A plastic cartridge holder for restraining and protecting data tape cartridges during shipping has individual cartridge slots with corrugated padding between adjacent slots and on the sides of the slots to decouple the cartridges from virtually any shock event. The cartridges do not separate or fall apart from each other when the external bundling material or shrink-wrapping is removed. The corrugations and slots hold the cartridges in place with a retention force that is firm yet comfortable for the user to overcome. The slots on the beveled corners allow individual cartridge actuation of access doors for inspection of the tape leader pins before the cartridges are removed. The opposite side of the holder has a full, cartridge-length access to the individual slots. The holder also has an access slot to allow the user to manually push all of the cartridges out of the holder simultaneously.

Abstract: A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.

Abstract: A structure and method to prevent barrier failure is provided. The present invention replaces a standard titanium-nitride (TiN) barrier metal layer with two separately-formed TiN layers. The two TiN layers provide smaller, mismatched grain boundaries. During subsequent tungsten deposition using WF6, the WF6 finds it difficult to penetrate through the mismatched grain boundaries, thereby minimizing any possibility of “tungsten volcano”. One embodiment includes a native or a grown oxide formed between the two TiN layers, thereby providing yet another diffusion barrier to the WF6 and acting as a glue layer between the two TiN layers. The present invention provides a thin and strong barrier metal layer with minimal barrier failures.

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells.

Abstract: A method of forming a bond pad area for an integrated circuit provides FSG in the dielectric layer while at the same time minimizes bond pad lift off. The method includes forming a first dielectric layer of fluorinated silicon glass (FSG) on a substrate, then forming an FSG barrier layer on the first dielectric layer. A second, non-FSG dielectric layer is formed on the FSG barrier layer. A barrier metal layer is then formed on the second dielectric layer. Finally, a metal layer is formed on the barrier metal layer. This metal layer provides the surface for adhesion to the bonding wire. The FSG barrier layer absorbs the atoms of fluorine diffused from the first dielectric layer. In this manner, fluorine is prevented from penetrating the second dielectric layer, thereby minimizing bond pad lift off between the second dielectric layer and the barrier metal layer. In one embodiment, the FSG barrier layer includes titanium and/or aluminum.

Abstract: A structure and method to prevent barrier failure is provided. The present invention replaces a standard titanium-nitride (TiN) barrier metal layer with two separately-formed TiN layers. The two TiN layers provide smaller, mismatched grain boundaries. During subsequent tungsten deposition using WF6, the WF6 finds it difficult to penetrate through the mismatched grain boundaries, thereby minimizing any possibility of “tungsten volcano”. One embodiment includes a native or a grown oxide formed between the two TiN layers, thereby providing yet another diffusion barrier to the WF6 and acting as a glue layer between the two TiN layers. The present invention provides a thin and strong barrier metal layer with minimal barrier failures.

Abstract: A three terminal non-volatile memory element includes a standard (low voltage) CMOS transistor, i.e. a storage transistor, having a drain coupled to a read bit line and a source connected to ground. The storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. Of importance, in submicron technology, the source and drain regions of the storage transistor merge, thereby providing a highly reliable, conductive path. Thus, the state of the memory cell can be advantageously read solely via the read bit line.