Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described.

Abstract: A circuit for enabling the discharge of electric charge in an integrated circuit is described. The circuit comprises an input/output pad coupled to a first node; a first diode coupled between the first node and a ground node; a transistor coupled in parallel with the first diode between the first node and ground node; and a resistor coupled between a body portion of the transistor and the ground node. A method of enabling the discharge of electric charge is also described.

Abstract: An electrostatic discharge (ESD) protection circuit for high-voltage power rails includes an RC-triggered clamp, one or more first forward-biased diodes coupled in series between a supply node and the first node; and one or more second forward-biased diodes coupled in series between the first node and the third node. The RC-triggered clamp includes: an RC-circuit having a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a third node; a transistor with a first source/drain, a gate, and a second source/drain; and an inverter. The first source/drain of the transistor is coupled to the first node, and the second source/drain is coupled to the third node. An input of the inverter is coupled to the second node, and an output of the inverter is coupled to the gate of the transistor.

Abstract: A circuit includes a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate and an n-well implemented within the p-type substrate that is independent of the storage element. The n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well.

Abstract: A memory array having improved radiation immunity is described. The memory array comprises a plurality of memory elements, each memory element having an p-type transistor formed in an n-type region; and a plurality of p-wells, each p-well having an n-type transistor coupled to a corresponding p-type transistor to form a memory element of the plurality of memory elements; wherein each p-well provides a p-n junction to dissipate minority charge in a portion of the n-type region occupied by a corresponding p-type transistor and associated with at least two adjacent memory elements. A method of implementing a memory array is also described.

Abstract: Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.

Abstract: A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.

Abstract: Enhanced electrostatic discharge (“ESD”) protection for an integrated circuit is described. An embodiment relates generally to a circuit for protection against ESD. The circuit has an input/output node and a driver. The driver has a first transistor and a second transistor. A first source/drain node of the first transistor is coupled to the input/output node. A second source/drain node of the first transistor forms a first interior node capable of accumulating charge when electrically floating. A first current flow control circuit is coupled to a discharge node and the second source/drain node of the first transistor. The first current flow control circuit is electrically oriented in a bias direction for allowing accumulated charge to discharge from the first interior node via the first current flow control circuit to the discharge node.

Abstract: A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.

Abstract: An embodiment of a semiconductor structure for an electrostatic discharge (“ESD”) protection circuit is disclosed. For this embodiment, there is a substrate of a first polarity type. A device area of the substrate has a source region and a drain region of a transistor. The device area is of the first polarity type, and the source region and the drain region are each of a second polarity type. A well region of the second polarity type surrounds the device area. An outer tap of the first polarity type surrounds the well region, and a bridge interconnects the source region and the outer tap.

Abstract: Provided herein are ergonomic impact damage resistant protector devices, and methods of use thereof. The protector devices are configured to be adapted to the edges, corners and/or boundary regions of an article having defined edges, boundaries and/or corners. Particularly, the disclosure is directed to impact damage resistant protector devices positioned substantially at boundaries, edges and corners of an article whereby the adaptation of the protector devices onto the article will effectively serve as a shock absorber and/or impact diffuser thereby preventing external impact forces from being transmitted internally to the article.

Abstract: An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described.

Abstract: Approaches for operating a programmable integrated circuit (IC) are disclosed. One configuration bitstream of two or more configuration bitstreams is selected. Each configuration bitstream implements a functionally equivalent circuit on the programmable IC and programs a respective subset of pass gates of the programmable IC. Each subset of pass gates programmed by the configuration bitstreams is disjoint from each other subset of pass gates. The programmable IC, which is defect-free, is configured with the selected configuration bitstream. The defect-free programmable IC is then operated for a period of time. The selecting, configuring and operating are repeated, and for successive selecting operations, different ones of the configuration bitstreams are selected.

Abstract: In accordance with some embodiments, an electrostatic discharge (ESD) protection circuit for high-voltage power rails includes an RC-triggered clamp having an RC-circuit having a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a third node. The RC-triggered clamp also has a transistor with a first source/drain, a gate, and a second source/drain, wherein the first source/drain is coupled to the first node, and the second source/drain is coupled to the third node. The RC-triggered clamp also has an inverter, wherein an input of the inverter is coupled to the second node, and an output of the inverter is coupled to the gate of the transistor. The ESD protection circuit also includes one or more forward-biased diodes coupled in series between a supply node and the first node.

Abstract: A sealing device includes a base member configured to attach to an ink developer unit, a sealing member having a sealing surface configured to at least one of limit an unwanted flow of ink outside of the ink developer unit and conform to an outer surface of a respective roller, and a compliant member disposed between the base member and the sealing member such that the compliant member is configured to vary a sealing force along the sealing surface of the sealing member.

Abstract: An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.

Abstract: An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.

Abstract: An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.

Abstract: An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.