Abstract: A circuit for implementing a discharge path in an input/output circuit of an integrated circuit is described. The circuit comprises an input/output pad; a first node coupled to a power reference voltage; a first impedance element implemented between the first node and the input/output pad; a second node coupled to a ground reference voltage; and a second impedance element implemented between the second node and the input/output pad. A method of implementing a discharge path in an input/output circuit of an integrated circuit is also disclosed.

Abstract: Methods and apparatus are described for detecting both single event latch-up (SEL) and electrical overvoltage stress (EOS) using a single, reconfigurable detection circuit. One example circuit capable of detecting a latch-up state and an overvoltage condition generally includes an impedance element coupled to a power supply node; a voltage divider coupled to the power supply node; a multiplexer having a first input coupled to a tap of the voltage divider, a second input coupled to a first portion of the impedance element, and a third input coupled to a second portion of the impedance element; a reference generator; and an analog-to-digital converter (ADC) having a first input coupled to an output of the multiplexer and a second input coupled to an output of the reference generator.

Abstract: A method of digitizing an audio track carried on an elongate recording medium, such as a movie film, includes transporting the recording medium containing the audio track past a reader to enable sequential reading of the audio track. The reading of the audio track generates an analog output signal. The method also includes sensing a rate of transportation of the recording medium, and sampling the analog output signal at a sampling rate determined on the basis of the sensed rate of transportation to digitize the analog output signal. A system for digitizing audio is also disclosed.

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors for coupling an integrated circuit die to the interposer to provide a stacked die. The interposer includes a pad coupled to a conductive network of the interposer to dissipate electrostatic charge from the interposer.

Abstract: A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.

Abstract: Embodiments herein describe techniques for wafer to wafer stacking of integrated circuit chips (e.g., dice) to form stacked IC devices. In one example, a stacked IC device is provided that includes a first wafer, a second wafer, and first conductive bridge. The second wafer is stacked on and secured to the first wafer. The second wafer has a plurality of IC dice that are communicatively coupled to a plurality of IC dice formed on the first wafer. The first conductive bridge has a first end that is sandwiched between the first and second wafers. The first conductive bridge shorts exposed pads of dice formed in the exclusion zones of the first and second wafers.

Abstract: Various example implementations are directed to circuits and methods for inter-die communication on a multi-die integrated circuit (IC) package. According to an example implementation, an IC package includes a first semiconductor die having a plurality of communication circuits for communicating data over respective data terminals of the package. The package also includes a second semiconductor die having N contacts for communicating data to and from the semiconductor die. The second semiconductor die includes a logic circuit configured to communicate M parallel data signals with one or more other semiconductor dies of the package, wherein M>N. The second semiconductor die also includes a plurality of serializer circuits, each configured to serialize data from a respective subset of the plurality of the M signal lines to produce serialized data and provide the serialized data to a respective one of the contacts.

Abstract: A system configured for detecting electrical overstress events within an integrated circuit includes a comparator configured to determine whether a monitored voltage level of a monitored signal exceeds an overstress reference voltage level. The overstress reference voltage level is a predetermined amount of voltage above a nominal voltage level for the monitored signal. The system further includes a write circuit coupled to an output of the comparator. The write circuit is configured to indicate an occurrence of an electrical overstress event within the integrated circuit responsive to the comparator determining that the monitored voltage level exceeds the overstress reference voltage level.

Abstract: In accordance with some embodiments, an electrostatic discharge (ESD) protection circuit for high-voltage power rails includes an RC-triggered clamp having an RC-circuit having a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a third node. The RC-triggered clamp also has a transistor with a first source/drain, a gate, and a second source/drain, wherein the first source/drain is coupled to the first node, and the second source/drain is coupled to the third node. The RC-triggered clamp also has an inverter, wherein an input of the inverter is coupled to the second node, and an output of the inverter is coupled to the gate of the transistor. The ESD protection circuit also includes one or more forward-biased diodes coupled in series between a supply node and the first node.

Abstract: Determining a circuit design-specific, failures in time rate for single event upsets for an integrated circuit (IC) includes determining, using a processor, a number of critical interconnect multiplexer bits for a circuit design for a target IC and determining a number of critical look-up table bits for the circuit design. Using the processor, a device vulnerability factor is estimated for the circuit design for the target IC using the number of critical interconnect multiplexer bits and the number of critical look-up table bits. The estimated device vulnerability factor can be stored, e.g., for subsequent comparison with other circuit designs.

Abstract: Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory.

Abstract: Various example implementations are directed to circuits and methods for inter-die communication on a multi-die integrated circuit (IC) package. According to an example implementation, an IC package includes a first semiconductor die having a plurality of communication circuits for communicating data over respective data terminals of the package. The package also includes a second semiconductor die having N contacts for communicating data to and from the semiconductor die. The second semiconductor die includes a logic circuit configured to communicate M parallel data signals with one or more other semiconductor dies of the package, wherein M>N. The second semiconductor die also includes a plurality of serializer circuits, each configured to serialize data from a respective subset of the plurality of the M signal lines to produce serialized data and provide the serialized data to a respective one of the contacts.

Abstract: A circuit for providing a ground path in an integrated circuit device is described. The circuit comprises a device region formed in a substrate; a substrate tap formed adjacent to the device region; and a conductive path coupled between the substrate tap and a ground metal layer by way of a plurality of metal layers and vias, wherein the conductive path is configured to meet a predetermined design requirement.

Abstract: An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.

Abstract: According to a method of preparing a layout of semiconductor circuit elements, a computer processor determines a first value of a distance metric that describes a separation between at least one well of a first type and at least one well of a second type in a first layout of a circuit design represented in a memory coupled to the computer processor. The at least one well of the first type and the at least one well of the second type are rearranged into a second layout. The method determines a second value of the distance metric that describes separation between the at least one well of the first type and the at least one well of the second type in the second layout. The second layout is stored in response to the second value of the distance metric being greater than the first value of the distance metric.

Abstract: An integrated circuit device having improved radiation immunity is described. The integrated circuit device comprises an n-type wafer having a first surface and a second surface; a p-type epitaxial layer formed on the first surface of the n-type wafer, the p-type epitaxial wafer having first elements storing charge; and an n-well formed in the p-type epitaxial layer, the n-well having second elements storing charge; wherein the n-type wafer is positively biased to attract excess minority carriers in the p-type epitaxial layer. A method of improving radiation immunity in an integrated circuit is also described.

Abstract: To implement a circuit design on a programmable integrated circuit (IC), first data are generated for implementing the circuit design. Critical and non-critical portions of the circuit design are determined, and second data are generated for programming configuration memory cells of the programmable IC to implement the circuit design. A first subset of the second data is assigned to program a first type of configuration memory cells to implement the critical portion of the circuit design on a first subset of programmable logic resources and a first subset of programmable interconnect resources of the programmable IC. A second subset of the second data is assigned to program a second type of configuration memory cells to implement the non-critical portion of the circuit design on a second subset of programmable logic resources and a second subset of programmable interconnect resources. The second data are stored in an electronically readable storage medium.

Abstract: A sealing device includes a base member configured to attach to an ink developer unit, a sealing member having a sealing surface configured to at least one of limit an unwanted flow of ink outside of the ink developer unit and conform to an outer surface of a respective roller, and a compliant member disposed between the base member and the sealing member such that the compliant member is configured to vary a sealing force along the sealing surface of the sealing member.

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.

Abstract: A method and apparatus to provide a power segmentation architecture that substantially eliminates the routing and area penalties associated with conventional power segmentation architectures. Power switching components are configured within the external interconnect portion of the integrated circuit (IC) to reduce the number of inter-layer interconnects that must be traversed in order to programmably supply operational power to the various device segments of the IC. A system-in-package (SIP) integration approach is alternately taken, whereby the power switching components utilized within the power segmentation architecture are conveniently allocated among the base or stacked die to reduce the number of inter-layer interconnects. The power switching components may also be implemented off-chip as discrete switching components such as a transistor or a micro-miniature switch/relay.