Patents by Inventor Jea-gun Park
Jea-gun Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210210531Abstract: The present invention discloses an image sensor including a quantum dot layer. The image sensor including a quantum dot layer according to the present invention includes photoelectric conversion elements formed on a substrate to correspond to a plurality of pixel regions; a wiring layer formed on the substrate on which the photoelectric conversion elements are formed; color filters formed on the wiring layer to correspond to the photoelectric conversion elements; and a quantum dot layer formed on the color filters and absorbing light and emitting visible light having a specific range of wavelengths converted from the absorbed light.Type: ApplicationFiled: April 20, 2018Publication date: July 8, 2021Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Il Hwan KIM, Jun Seong PARK, Yun Hyuk KOH
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Patent number: 11050014Abstract: A memory device contains lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode, which are formed on a substrate in a laminated manner. In the memory device, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.Type: GrantFiled: March 18, 2015Date of Patent: June 29, 2021Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee, Min Su Jeon, Jong Ung Baek, Tae Hun Shim
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Publication number: 20210195077Abstract: The present invention discloses a dual image sensor. The dual image sensor according to one embodiment of the present invention includes first and second image sensor modules mounted on a printed circuit board, wherein the first image sensor module includes a first housing mounted on the printed circuit board; a first image sensor mounted on the printed circuit board and formed on a first surface of the first housing; and a first lens formed on a second surface of the first housing, and the second image sensor module includes a second housing mounted on the printed circuit board; a second image sensor mounted on the printed circuit board and formed on a first surface of the second housing; a second lens formed on a second surface of the second housing; and a quantum dot layer formed between the second image sensor and the second lens and absorbing ultraviolet light and emitting visible light converted from the absorbed ultraviolet light.Type: ApplicationFiled: April 20, 2018Publication date: June 24, 2021Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Il Hwan KIM, Jun Seong PARK, Ji Ho CHOI
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Publication number: 20210135091Abstract: Disclosed is a memory device including a multi-bit perpendicular magnetic tunnel junction, wherein the multi-bit perpendicular magnetic tunnel junction includes an upper synthetic antiferromagnetic layer, pinned layer, lower dual free layer, and upper free layer formed in a laminated manner between a top electrode and a bottom electrode.Type: ApplicationFiled: November 19, 2019Publication date: May 6, 2021Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Jong Ung BAEK, Kei ASHIBA, Jin Young CHOI, Mi Ri PARK, Hyun Gyu LEE, Han Sol JUN, Sun Hwa JUNG
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Patent number: 10998515Abstract: The present invention provides a solar cell and a method for manufacturing the same, the solar cell including a first electrode formed on a substrate, a nanocrystal layer including a plurality of nanocrystals formed on the first electrode so as to contact the first electrode, a hole transport layer formed on the first electrode so as to cover the plurality of nanocrystals, a photoactive layer formed on the hole transport layer, and a second electrode formed on the photoactive layer.Type: GrantFiled: October 10, 2014Date of Patent: May 4, 2021Inventors: Jea Gun Park, Tea Hun Shim, Dal Ho Kim, Ji Heon Kim, Jae Woo Shin, Joo Hyoung Park
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Patent number: 10886274Abstract: The present invention discloses a two-terminal vertical 1T-DRAM and a method of fabricating the same. According to one embodiment of the present invention, the two-terminal vertical 1T-DRAM includes a cathode layer formed of a first-type high-concentration semiconductor layer; a base region including a second-type low-concentration semiconductor layer formed on the cathode layer and a first-type low-concentration semiconductor layer formed on the second-type low-concentration semiconductor layer; and an anode layer formed of a second-type high-concentration semiconductor layer on the first-type low-concentration semiconductor layer.Type: GrantFiled: November 30, 2017Date of Patent: January 5, 2021Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Seung Hyun Song, Min Won Kim
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Publication number: 20200381570Abstract: Provided here nontoxic CuGaS2/ZnS core/shell nanocrystals with free-self-reabsorption losses and large Stokes shift synthesized on an industrially gram-scale. The nanocrystals exhibited a typical energy-down-shift that absorbs only ultraviolet light and emits the whole range of visible light with a high photoluminescence-quantum yield. The straightforward application of these energy-down-shift nanocrystals on the front surface of a monocrystalline p-type silicon solar cell significantly enhanced the short-circuit current density and power conversion efficiency. The significant improvement in the external quantum efficiency and that decreasing in the surface reflectance in the ultraviolet region clearly manifest the photovoltaic enhancement.Type: ApplicationFiled: May 10, 2020Publication date: December 3, 2020Inventors: Mohammed Jalalah, Mohammad Sultan Al-Assiri, Jea-Gun Park
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Patent number: 10854254Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.Type: GrantFiled: November 1, 2019Date of Patent: December 1, 2020Assignee: IUCF-HYU (INDUSTRY—UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)Inventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee
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Publication number: 20200357450Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.Type: ApplicationFiled: November 1, 2019Publication date: November 12, 2020Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Du Yeong Lee, Seung Eun Lee
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Publication number: 20200350489Abstract: Disclosed is a memory device. A memory device according to an embodiment of the present invention includes a memory device including a substrate; and a lower electrode, seed layer, lower synthetic antiferromagnetic layer, magnetic tunnel junction, upper synthetic antiferromagnetic layer, and upper electrode that are laminated on the substrate, wherein the magnetic tunnel junction includes a lower pinned layer, lower tunnel barrier layer, lower free layer, separation layer, upper free layer, upper tunnel barrier layer and upper pinned layer that are sequentially laminated.Type: ApplicationFiled: January 4, 2019Publication date: November 5, 2020Applicant: IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)Inventors: Jea Gun PARK, Jin Young CHOI, Han Sol JUN, Dong Gi LEE, Kondo KEI, Jong Ung BAEK
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Patent number: 10783945Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.Type: GrantFiled: November 18, 2019Date of Patent: September 22, 2020Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)Inventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee
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Publication number: 20200266333Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.Type: ApplicationFiled: March 18, 2015Publication date: August 20, 2020Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Du Yeong LEE, Seung Eun LEE, Min Su JEON, Jong Ung BAEK, Tae Hun SHIM
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Patent number: 10643681Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic (SyAF) layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, SyAF layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the SyAF layers to grow in the FCC (111) direction.Type: GrantFiled: April 19, 2019Date of Patent: May 5, 2020Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)Inventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee
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Publication number: 20200090720Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.Type: ApplicationFiled: November 18, 2019Publication date: March 19, 2020Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITYInventors: Jea Gun PARK, Du Yeong LEE, Seung Eun LEE
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Patent number: 10586919Abstract: A memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. The lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.Type: GrantFiled: March 18, 2015Date of Patent: March 10, 2020Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee, Min Su Jeon, Jong Ung Baek, Tae Hun Shim
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Patent number: 10580964Abstract: The present invention relates to a memory device including a substrate and a lower electrode, buffer layer, seed layer, Magnetic Tunnel Junction (MTJ), capping layer, synthetic antiferromagnetic layer, and upper electrode formed on the substrate.Type: GrantFiled: September 18, 2017Date of Patent: March 3, 2020Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Du Yeong Lee, Song Hwa Hong, Jin Young Choi, Seung Eun Lee, Junli Li
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Publication number: 20200066319Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.Type: ApplicationFiled: November 1, 2019Publication date: February 27, 2020Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Du Yeong Lee, Seung Eun Lee
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Publication number: 20200027882Abstract: The present invention discloses a two-terminal vertical 1T-DRAM and a method of fabricating the same. According to one embodiment of the present invention, the two-terminal vertical 1T-DRAM includes a cathode layer formed of a first-type high-concentration semiconductor layer; a base region including a second-type low-concentration semiconductor layer formed on the cathode layer and a first-type low-concentration semiconductor layer formed on the second-type low-concentration semiconductor layer; and an anode layer formed of a second-type high-concentration semiconductor layer on the first-type low-concentration semiconductor layer.Type: ApplicationFiled: November 30, 2017Publication date: January 23, 2020Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Seung Hyun SONG, Min Won KIM
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Patent number: 10516097Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.Type: GrantFiled: March 18, 2015Date of Patent: December 24, 2019Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee, Min Su Jeon, Jong Ung Baek, Tae Hun Shim
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Patent number: 10510532Abstract: Disclosed is a method of fabricating a gallium nitride substrate using a plurality of ion implantation processes.Type: GrantFiled: May 29, 2018Date of Patent: December 17, 2019Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Jae Hyoung Shim, Tae Hun Shim