Abstract: Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.

Abstract: A slurry composition for chemical-mechanical polishing capable of compensating nanotopography effect present on the surface of a wafer, and a method for planarizing the surface of a semiconductor device that utilizes the same are disclosed. The slurry composition of the present invention is aimed at compensating the nanotopography effect during chemical mechanical polishing process of the oxide layer formed on the surface of the wafer, and contains abrasive particles and an additive, wherein the size of the abrasive particles and the concentration of the additive are controlled within predetermined ranges in order to control the deviation of thickness (OTD) of the oxide layer below a certain level after the chemical mechanical polishing process.

Abstract: Provided are a luminescent device and a method of manufacturing the same. The luminescent device includes a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping layer.

Abstract: Disclosed is a slurry for polishing a phase change material. The slurry includes an abrasive, an alkaline polishing promoter and deionized water. Due to the use of the abrasive and the alkaline polishing promoter, the pH of the slurry is adjusted, the polishing rate of the phase change material is improved, and the polishing selectivity of the phase change material to an underlying insulating layer is increased. Further disclosed is a method for patterning a phase change material using the slurry.

Abstract: The present invention relates to a flexible single-crystal film and a method of manufacturing the same from a single-crystal wafer. That is, the present invention can manufacture a silicon-on-insulator (SOI) wafer comprising a base wafer, one or more buried insulator layers, and a single-crystal layer into a flexible single-crystal film with a desired thickness by employing various wafer thinning techniques. The method for manufacturing a flexible film comprises the steps of (i) providing a SOI wafer comprising a base wafer, one or more buried insulator layers on the base wafer, and a single-crystal layer on said one or more buried insulator layers, (ii) forming one or more protective insulator layers on said single-crystal layer, (iii) removing said base wafer, and (iv) removing one or more of the insulator layers.

Abstract: Disclosed is a polishing slurry, particularly, a slurry for chemical mechanical polishing, which is used in a chemical mechanical polishing process for flattening a semiconductor laminate. More particularly, the present invention provides a method of producing a slurry which has high removal selectivity to a nitride layer used as a barrier film in a shallow trench isolation CMP process needed to fabricate ultra highly integrated semiconductors of 256 mega D-RAM or more (Design rule of 0.13 ?m or less) and which decreases the occurrence of scratches on a flattened surface, and a method of polishing a substrate using the same.

Abstract: Disclosed is a polishing slurry, particularly, a slurry for chemical mechanical polishing, which is used in a chemical mechanical polishing process for flattening a semiconductor laminate. More particularly, the present invention provides a method of producing a slurry which has high removal selectivity to a nitride layer used as a barrier film in a shallow trench isolation CMP process needed to fabricate ultra highly integrated semiconductors of 256 mega D-RAM or more (Design rule of 0.13 ?m or less) and which decreases the occurrence of scratches on a flattened surface, and a method of polishing a substrate using the same.

Abstract: The present invention provides a bonded substrate fabricated to have its final active layer thickness of 200 nm or lower by performing the etching by only 1 nm to 1 ?m with a solution having an etching effect on a surface of an active layer of a bonded substrate which has been prepared by bonding two substrates after one of them having been ion-implanted and then cleaving off a portion thereof by heat treatment. SC-1 solution is used for performing the etching. A polishing, a hydrogen annealing and a sacrificial oxidation may be respectively applied to the active layer before and/or after the etching. The film thickness of this active layer can be made uniform over the entire surface area and the surface roughness of the active layer can be reduced as well.

Abstract: A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation.

Abstract: A nonvolatile memory device and a method of manufacturing the same are provided. The nonvolatile memory device which is convertible among a high current state, an intermediate current state, and a low current state, said device includes upper and lower conductive layers; a conductive organic layer comprising a conductive organic polymer and which is formed between the upper and lower conductive layers and has a bistable conduction property; and nanocrystals are formed in the conductive organic layer. The conductive organic polymer may be poly-N-vinylcarbazole (PVK) or polystyrene (PS). The method is characterized in that a conductive organic layer is formed by applying a conductive organic material such as PVK or PS using spin coating. Therefore, it is possible to provide a highly-integrated memory device that consumes less power and provides high operating speed. In addition, it is possible to provide the thermal stability of a memory device by using a conductive organic polymer.

Abstract: The method of manufacturing a nonvolatile memory device includes forming a lower conductive layer on a substrate; forming a first conductive organic layer on the substrate using spin coating; forming a metal layer for forming nanocrystals on the first conductive organic layer, the metal layer partially overlapping the first conductive organic layer; forming a second conductive organic layer on the first conductive organic layer using spin coating; transforming the metal layer into nanocrystals by curing; and forming an upper conductive layer on the second conductive organic layer, the upper conductive layer partially overlapping the nanocrystals. The conductive organic polymer may be poly-N-vinylcarbazole (PVK) or polystyrene (PS).

Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.

Abstract: The present invention relates to a CMP abrasive comprising a ceria slurry and a chemical additive having two or more functional groups by mixing and synthesizing a polymeric molecule and a monomer. Also, the present invention relates to a method for a manufacturing CMP abrasive by providing a ceria slurry, manufacturing a chemical additive having two or more functional groups by mixing and synthesizing of the polymeric molecule and the monomer in a reactor, and mixing said slurry and said chemical additive. Therefore, when the abrasive according to the present invention is used as an STI CMP abrasive, it is possible to apply the abrasive to the patterning process required in the very large scale integration semiconductor process. Furthermore, the CMP abrasive of the present invention has a superior removal rate, superior polishing selectivity, superior within wafer non-uniformity (WIWNU), and minimized occurrence of micro scratches.

Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.

Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.

Abstract: A silicon wafer is provided having controlled distribution of defects, in which denuded zones having a sufficient depth inward from the surface of the wafer are combined with a high gettering effect in a bulk region of the wafer. In the silicon wafer, oxygen precipitates, which act as intrinsic gettering sites, show vertical distribution. The oxygen precipitate concentration profile from the top to the bottom surfaces of the wafer includes first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, denuded zones between the top and bottom surfaces of the wafer and each of the first and second peaks, and a concave region between the first and second peaks, which corresponds to a bulk region of the wafer. For such an oxygen precipitate concentration profile, the wafer is exposed to a rapid thermal annealing process in a gas mixture atmosphere containing nitrogen (N2) and argon (Ar) or N2 and hydrogen (H2), in a donor killing step during a wafering process.

Abstract: The present invention relates to a flexible single-crystal film and a method of manufacturing the same from a single-crystal wafer. That is, the present invention can manufacture a silicon-on-insulator (SOI) wafer comprising a base wafer, one or more buried insulator layers, and a single-crystal layer into a flexible single-crystal film with a desired thickness by employing various wafer thinning techniques. The method for manufacturing a flexible film comprises the steps of (i) providing a SOI wafer comprising a base wafer, one or more buried insulator layers on the base wafer, and a single-crystal layer on said one or more buried insulator layers, (ii) forming one or more protective insulator layers on said single-crystal layer, (iii) removing said base wafer, and (iv) removing one or more of the insulator layers.

Abstract: The present invention relates to a flexible electro-optical apparatus such as a flexible high-resolution liquid crystal display wherein single-crystal silicon semiconductor is used in manufacturing driver circuits and pixel arrays, and a method for manufacturing the same. The flexible electro-optical apparatus according to the present invention comprises a flexible lower substrate portion including device layers where electronic devices are formed on a flexible single-crystal layer; a flexible upper substrate portion to be bonded to said lower substrate portion; and an electro-optical layer between said lower substrate portion and said upper substrate portion.

Abstract: A silicon wafer is provided having controlled distribution of defects, in which denuded zones having a sufficient depth inward from the surface of the wafer are combined with a high gettering effect in a bulk region of the wafer. In the silicon wafer, oxygen precipitates, which act as intrinsic gettering sites, show vertical distribution. The oxygen precipitate concentration profile from the top to the bottom surfaces of the wafer includes first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, denuded zones between the top and bottom surfaces of the wafer and each of the first and second peaks, and a concave region between the first and second peaks, which corresponds to a bulk region of the wafer. For such an oxygen precipitate concentration profile, the wafer is exposed to a rapid thermal annealing process in a gas mixture atmosphere comprising ammonia (NH3) and argon (Ar) at temperatures below about 1200° C.

Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.