Patents by Inventor Jeehwan Kim

Jeehwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONTROLLABLE INDIUM DOPING FOR HIGH EFFICIENCY CZTS THIN-FILM SOLAR CELLS
    Publication number: 20160359076
    Abstract: A photovoltaic device includes a first contact layer formed on a substrate. An absorber layer includes Cu—Zn—Sn—S(Se) (CZTSSe) on the first contact layer. A buffer layer is formed in contact with the absorber layer. Metal dopants are dispersed in a junction region between the absorber layer and the buffer layer. The metal dopants have a valence between the absorber layer and the buffer layer to increase junction potential. A transparent conductive contact layer is formed over the buffer layer.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 8, 2016
    Inventors: Talia S. Gershon, Jeehwan Kim, Yun Seog Lee, Teodor K. Todorov
  • FORMATION OF DISLOCATION-FREE SiGe FINFET USING POROUS SILICON
    Publication number: 20160359044
    Abstract: A semiconductor device that includes a fin structure having a porous core, and a relaxed semiconductor layer present on the porous core. The semiconductor device may further include a strained semiconductor layer that is substantially free of defects that is present on the strained semiconductor layer. A gate structure may be present on a channel region of the fin structure, and source and drain regions may be present on opposing sides of the gate structure.
    Type: Application
    Filed: June 4, 2015
    Publication date: December 8, 2016
    Inventors: Stephen W. Bedell, Kangguo Cheng, Jeehwan Kim, Alexander Reznicek, Devendra K. Sadana
  • HYBRID CZTSSe PHOTOVOLTAIC DEVICE
    Publication number: 20160359072
    Abstract: A photovoltaic device includes a first contact and a hybrid absorber layer. The hybrid absorber layer includes a chalcogenide layer and a semiconductor layer in contact with the chalcogenide layer. A buffer layer is formed on the absorber layer, and a transparent conductive contact layer is formed on the buffer layer.
    Type: Application
    Filed: August 11, 2016
    Publication date: December 8, 2016
    Inventors: Tayfun Gokmen, Oki Gunawan, Richard A. Haight, Jeehwan Kim, David B. Mitzi, Mark T. Winkler
  • Efficiency restoration in a photovoltaic cell
    Patent number: 9515215
    Abstract: The electrical output efficiency of a photovoltaic thermal system can be restored from degradation due to light exposure by annealing a photovoltaic thermal cell at an elevated temperature. The elevated temperature at the photovoltaic thermal cell can be provided by redirecting the flow of a heat exchange fluid to bypass a heat exchanger unit. A boiler unit may be employed to provide additional heating of the heat exchange fluid during the anneal. Further, a variable configuration lid can be provided over a front surface of the photovoltaic thermal cell to control ventilation over the front surface. During the anneal, the position of the variable configuration lid can be set so as to trap heat above the front surface and to elevate the anneal temperature further.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: December 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Young T. Chae, Augustin J. Hong, Jeehwan Kim, Young M. Lee, Devendra K. Sadana
  • HIGHLY RESPONSIVE III-V PHOTODETECTORS USING ZnO:Al AS N-TYPE EMITTER
    Publication number: 20160351728
    Abstract: A photodiode includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. An intrinsic layer is formed over the substrate and including a III-V material. A transparent II-VI n-type layer is formed on the intrinsic layer and functions as an emitter and an n-type ohmic contact.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 1, 2016
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Brent A. Wacaser
  • DRY ETCH METHOD FOR TEXTURING SILICON AND DEVICE
    Publication number: 20160351733
    Abstract: A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 1, 2016
    Inventors: Talia S. Gershon, Richard A. Haight, Jeehwan Kim, Yun Seog Lee
  • DRY ETCH METHOD FOR TEXTURING SILICON AND DEVICE
    Publication number: 20160351734
    Abstract: A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 1, 2016
    Inventors: Talia S. Gershon, Richard A. Haight, Jeehwan Kim, Yun Seog Lee
  • SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING
    Publication number: 20160351397
    Abstract: A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 1, 2016
    Inventors: Stephen W. Bedell, Joel P. De Souza, Jeehwan Kim, Devendra K. Sadana
  • PHOTOVOLTAIC DEVICES WITH AN INTERFACIAL BAND-GAP MODIFYING STRUCTURE AND METHODS FOR FORMING THE SAME
    Publication number: 20160343899
    Abstract: A Schottky-barrier-reducing layer is provided between a p-doped semiconductor layer and a transparent conductive material layer of a photovoltaic device. The Schottky-barrier-reducing layer can be a conductive material layer having a work function that is greater than the work function of the transparent conductive material layer. The conductive material layer can be a carbon-material layer such as a carbon nanotube layer or a graphene layer. Alternately, the conductive material layer can be another transparent conductive material layer having a greater work function than the transparent conductive material layer. The reduction of the Schottky barrier reduces the contact resistance across the transparent material layer and the p-doped semiconductor layer, thereby reducing the series resistance and increasing the efficiency of the photovoltaic device.
    Type: Application
    Filed: August 5, 2016
    Publication date: November 24, 2016
    Inventors: Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, George S. Tulevski, Ahmed Abou-Kandil, Hisham S. Mohamed, Mohamed Saad, Osama Tobail
  • REDUCTION OF DEFECT INDUCED LEAKAGE IN III-V SEMICONDUCTOR DEVICES
    Publication number: 20160336395
    Abstract: A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm?2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.
    Type: Application
    Filed: June 19, 2015
    Publication date: November 17, 2016
    Inventors: Joel P. de Souza, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES
    Publication number: 20160336424
    Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 17, 2016
    Inventors: JOEL P. de SOUZA, BAHMAN HEKMATSHOARTABARI, JEEHWAN KIM, SIEGFRIED L. MAURER, DEVENDRA K. SADANA
  • REDUCTION OF DEFECT INDUCED LEAKAGE IN III-V SEMICONDUCTOR DEVICES
    Publication number: 20160336408
    Abstract: A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm?2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.
    Type: Application
    Filed: April 21, 2016
    Publication date: November 17, 2016
    Inventors: Joel P. de Souza, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES
    Publication number: 20160336418
    Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 17, 2016
    Inventors: JOEL P. de SOUZA, BAHMAN HEKMATSHOARTABARI, JEEHWAN KIM, SIEGFRIED L. MAURER, DEVENDRA K. SADANA
  • LED light extraction enhancement enabled using self-assembled particles patterned surface
    Patent number: 9490455
    Abstract: A light emitting diode (LED) containing device including a light emitting diode (LED) structure, and a light transmissive substrate in contact with the LED structure. The light transmissive substrate has a texture surface tuned to include features with dimensions greater than a wavelength of light produced by the LED structure. In some embodiments, increasing the feature size of the texture to be comparable to the wavelength of light produced by the LED increases light extraction from the LED in comparison to when the feature size of the texture is substantially less or substantially larger than the wavelength of light.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: November 8, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Jeehwan Kim, Ning Li, Devendra K. Sadana
  • FinFET CMOS with Si NFET and SiGe PFET
    Patent number: 9484347
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim
  • DOUBLE LAYERED TRANSPARENT CONDUCTIVE OXIDE FOR REDUCED SCHOTTKY BARRIER IN PHOTOVOLTAIC DEVICES
    Publication number: 20160300965
    Abstract: A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 13, 2016
    Inventors: SHUN-MING CHEN, CHIEN-CHIH HUANG, JOEL P. DESOUZA, AUGUSTIN J. HONG, JEEHWAN KIM, CHIEN-YEH KU, DEVENDRA K. SADANA, CHUAN-WEN WANG
  • LOW RESISTANCE CONTACT FOR SEMICONDUCTOR DEVICES
    Publication number: 20160300925
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type layer includes ZnO. An aluminum contact is formed in direct contact with the ZnO of the n-type material to form an electronic device.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 13, 2016
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • Uniformly distributed self-assembled cone-shaped pillars for high efficiency solar cells
    Patent number: 9459797
    Abstract: A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES, INC
    Inventors: Christos Dimitrakopoulos, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
  • LED LIGHT EXTRACTION ENHANCEMENT ENABLED USING SELF-ASSEMBLED PARTICLES PATTERNED SURFACE
    Publication number: 20160276628
    Abstract: A light emitting diode (LED) containing device including a light emitting diode (LED) structure, and a light transmissive substrate in contact with the LED structure. The light transmissive substrate has a texture surface tuned to include features with dimensions greater than a wavelength of light produced by the LED structure. In some embodiments, increasing the feature size of the texture to be comparable to the wavelength of light produced by the LED increases light extraction from the LED in comparison to when the feature size of the texture is substantially less or substantially larger than the wavelength of light.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Inventors: Keith E. Fogel, Jeehwan Kim, Ning Li, Devendra K. Sadana
  • LED LIGHT EXTRACTION ENHANCEMENT ENABLED USING SELF-ASSEMBLED PARTICLES PATTERNED SURFACE
    Publication number: 20160276524
    Abstract: A light emitting diode (LED) containing device including a light emitting diode (LED) structure, and a light transmissive substrate in contact with the LED structure. The light transmissive substrate has a texture surface tuned to include features with dimensions greater than a wavelength of light produced by the LED structure. In some embodiments, increasing the feature size of the texture to be comparable to the wavelength of light produced by the LED increases light extraction from the LED in comparison to when the feature size of the texture is substantially less or substantially larger than the wavelength of light.
    Type: Application
    Filed: June 19, 2015
    Publication date: September 22, 2016
    Inventors: Keith E. Fogel, Jeehwan Kim, Ning Li, Devendra K. Sadana