Patents by Inventor Jeehwan Kim

Jeehwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THREE-DIMENSIONAL CONDUCTIVE ELECTRODE FOR SOLAR CELL
    Publication number: 20170288071
    Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.
    Type: Application
    Filed: June 14, 2017
    Publication date: October 5, 2017
    Inventors: KEITH E. FOGEL, AUGUSTIN J. HONG, JEEHWAN KIM, DEVENDRA K. SADANA
  • Leakage-free implantation-free ETSOI transistors
    Patent number: 9768254
    Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • HIGHLY RESPONSIVE III-V PHOTODETECTORS USING ZnO:Al AS N-TYPE EMITTER
    Publication number: 20170263788
    Abstract: A photodiode includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. An intrinsic layer is formed over the substrate and including a III-V material. A transparent II-VI n-type layer is formed on the intrinsic layer and functions as an emitter and an n-type ohmic contact.
    Type: Application
    Filed: May 24, 2017
    Publication date: September 14, 2017
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Brent A. Wacaser
  • BANDGAP GRADING OF CZTS SOLAR CELL
    Publication number: 20170250302
    Abstract: A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.
    Type: Application
    Filed: May 11, 2017
    Publication date: August 31, 2017
    Inventors: Talia S. Gershon, Marinus J.P. Hopstaken, Jeehwan Kim, Yun Seog Lee
  • Highly responsive III-V photodetectors using ZnO:Al as N-type emitter
    Patent number: 9748412
    Abstract: A photodiode includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. An intrinsic layer is formed over the substrate and including a III-V material. A transparent II-VI n-type layer is formed on the intrinsic layer and functions as an emitter and an n-type ohmic contact.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: August 29, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Brent A. Wacaser
  • Protective insulating layer and chemical mechanical polishing for polycrystalline thin film solar cells
    Patent number: 9741890
    Abstract: A method for forming a photovoltaic device includes forming an absorber layer with a granular structure on a conductive layer; conformally depositing an insulating protection layer over the absorber layer to fill in between grains of the absorber layer; and planarizing the protection layer and the absorber layer. A buffer layer is formed on the absorber layer, and a top transparent conductor layer is deposited over the buffer layer.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Supratik Guha, Jeehwan Kim, Mahadevaiyer Krishnan, Byungha Shin
  • Three-dimensional conductive electrode for solar cell
    Patent number: 9741880
    Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • III-V FINS BY ASPECT RATIO TRAPPING AND SELF-ALIGNED ETCH TO REMOVE ROUGH EPITAXY SURFACE
    Publication number: 20170229453
    Abstract: A semiconductor device that includes a fin structure of a type III-V semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type III-V semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure.
    Type: Application
    Filed: July 1, 2016
    Publication date: August 10, 2017
    Inventors: Kangguo Cheng, Jeehwan Kim
  • III-V FINS BY ASPECT RATIO TRAPPING AND SELF-ALIGNED ETCH TO REMOVE ROUGH EPITAXY SURFACE
    Publication number: 20170229579
    Abstract: A semiconductor device that includes a fin structure of a type III-V semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type III-V semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure.
    Type: Application
    Filed: February 8, 2016
    Publication date: August 10, 2017
    Inventors: Kangguo Cheng, Jeehwan Kim
  • Bandgap grading of CZTS solar cell
    Patent number: 9722120
    Abstract: A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Marinus J. P. Hopstaken, Jeehwan Kim, Yun Seog Lee
  • Doped zinc oxide as n+ layer for semiconductor devices
    Patent number: 9722033
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type layer is formed on or in the p-doped layer. The n-type layer includes ZnO on the p-doped layer to form an electronic device.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. DeSouza, Keith E. Fogel, Jeehwan Kim, Ko-Tao Lee, Devendra K. Sadana
  • SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES
    Publication number: 20170213736
    Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
    Type: Application
    Filed: April 10, 2017
    Publication date: July 27, 2017
    Inventors: JOEL P. de SOUZA, BAHMAN HEKMATSHOARTABARI, JEEHWAN KIM, SIEGFRIED L. MAURER, DEVENDRA K. SADANA
  • Dry etch method for texturing silicon and device
    Patent number: 9716195
    Abstract: A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Richard A. Haight, Jeehwan Kim, Yun Seog Lee
  • Low reflection electrode for photovoltaic devices
    Patent number: 9716207
    Abstract: A method for forming a photovoltaic device includes forming a photovoltaic absorption stack on a substrate including one or more of I-III-VI2 and I2-II-IV-VI4 semiconductor material. A transparent conductive contact layer is deposited on the photovoltaic absorption stack at a temperature less than 200 degrees Celsius. The transparent conductive contact layer has a thickness of about one micron and is formed on a front light-receiving surface. The surface includes pyramidal structures due to an as deposited thickness. The transparent conductive contact layer is wet etched to further roughen the front light-receiving surface to reduce reflectance.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: July 25, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Keith E. Fogel, Jeehwan Kim, David B. Mitzi, Mark T. Winkler
  • POROUS FIN AS COMPLIANT MEDIUM TO FORM DISLOCATION-FREE HETEROEPITAXIAL FILMS
    Publication number: 20170200603
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Application
    Filed: March 24, 2017
    Publication date: July 13, 2017
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • POROUS FIN AS COMPLIANT MEDIUM TO FORM DISLOCATION-FREE HETEROEPITAXIAL FILMS
    Publication number: 20170200604
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Application
    Filed: March 24, 2017
    Publication date: July 13, 2017
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Self-formation of high-density arrays of nanostructures
    Patent number: 9691847
    Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christos D. Dimitrakopoulos, Jeehwan Kim, Hongsik Park, Byungha Shin
  • JUNCTION INTERLAYER DIELECTRIC FOR REDUCING LEAKAGE CURRENT IN SEMICONDUCTOR DEVICES
    Publication number: 20170179230
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 22, 2017
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • LEAKAGE-FREE IMPLANTATION-FREE ETSOI TRANSISTORS
    Publication number: 20170179304
    Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • FINFET CMOS WITH Si NFET AND SiGe PFET
    Publication number: 20170170180
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin.
    Type: Application
    Filed: June 20, 2016
    Publication date: June 15, 2017
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim