Patents by Inventor Jeehwan Kim

Jeehwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TUNABLE SEMICONDUCTOR BAND GAP REDUCTION BY STRAINED SIDEWALL PASSIVATION
    Publication number: 20170040240
    Abstract: A semiconductor device includes a mesa structure having vertical sidewalls, the mesa structure including an active area comprising a portion of its height. A stressed passivation liner is formed on the vertical sidewalls of the mesa structure and over the portion of the active area. The stressed passivation liner induces strain in the active area to permit tuning of performance parameters of the mesa structure.
    Type: Application
    Filed: August 7, 2015
    Publication date: February 9, 2017
    Inventors: Christopher Heidelberger, Jeehwan Kim, Ning Li, Wencong Liu, Devendra K. Sadana
  • MOSFET WITH ULTRA LOW DRAIN LEAKAGE
    Publication number: 20170033203
    Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.
    Type: Application
    Filed: October 7, 2016
    Publication date: February 2, 2017
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • POROUS FIN AS COMPLIANT MEDIUM TO FORM DISLOCATION-FREE HETEROEPITAXIAL FILMS
    Publication number: 20170032963
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Application
    Filed: July 29, 2015
    Publication date: February 2, 2017
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • MOSFET WITH ULTRA LOW DRAIN LEAKAGE
    Publication number: 20170033180
    Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.
    Type: Application
    Filed: October 13, 2016
    Publication date: February 2, 2017
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • RESONANT CAVITY STRAINED III-V PHOTODETECTOR AND LED ON SILICON SUBSTRATE
    Publication number: 20170033261
    Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana
  • LEAKAGE-FREE IMPLANTATION-FREE ETSOI TRANSISTORS
    Publication number: 20170033177
    Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 2, 2017
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • METAL PARTICLE ENHANCED FORSTER RESONANCE ENERGY TRANSFER FOR ORGANIC OPTOELECTRONIC DEVICE
    Publication number: 20170033305
    Abstract: A photovoltaic device that includes an organic or quantum dot sensitizer layer for absorbing light spectra and providing excitons. The sensitizer layer may include metal particles embedded therein for increased exciton transfer efficiency. The photovoltaic device may further include a junction comprising an electron donor layer and electron acceptor layer for charge carrier transport.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, Ning Li, Kuen-Ting Shiu
  • Porous silicon relaxation medium for dislocation free CMOS devices
    Patent number: 9559120
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • OPTOELECTRONICS INTEGRATION BY TRANSFER PROCESS
    Publication number: 20170018715
    Abstract: A method for fabricating an optoelectronic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at the adhesion layer by mechanically yielding the adhesion layer. A conductive layer is applied to the material layer on a side opposite the release tape to form a transfer substrate. The transfer substrate is transferred to a target substrate to join the target substrate to the conductive layer of the transfer substrate. The release tape is removed from the material layer to form a top emission optoelectronic device.
    Type: Application
    Filed: September 29, 2016
    Publication date: January 19, 2017
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Tze-bin Song
  • FORMATION OF HOMOJUNCTION IN KESTERITE-BASED SEMICONDUCTORS
    Publication number: 20170018666
    Abstract: Kesterite-based homojunction photovoltaic devices are provided. The photovoltaic devices include a p-type semiconductor layer including a copper-zinc-tin containing chalcogenide compound and an n-type semiconductor layer including a silver-zinc-tin containing chalcogenide compound having a crystalline structure the same as a crystalline structure the copper-zinc-tin containing chalcogenide compound.
    Type: Application
    Filed: July 14, 2015
    Publication date: January 19, 2017
    Inventors: Talia S. Gershon, Oki Gunawan, Richard A. Haight, Jeehwan Kim
  • MONOLITHICALLY INTEGRATED LASER WITH LED PUMP
    Publication number: 20170018902
    Abstract: A laser structure includes a substrate, a buffer layer formed on the substrate and a light emitting diode (LED) formed on the buffer layer. A photonic crystal layer is formed on the LED. A monolayer semiconductor nanocavity laser is formed on the photonic crystal layer for receiving light through the photonic crystal layer from the LED, wherein the LED and the laser are formed monolithically and the LED acts as an optical pump for the laser.
    Type: Application
    Filed: July 14, 2015
    Publication date: January 19, 2017
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Brent A. Wacaser
  • POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES
    Publication number: 20170005113
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Application
    Filed: July 2, 2015
    Publication date: January 5, 2017
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • ALUMINUM-DOPED ZINC OXYSULFIDE EMITTERS FOR ENHANCING EFFICIENCY OF CHALCOGENIDE SOLAR CELL
    Publication number: 20170005210
    Abstract: A photovoltaic device includes a substrate, a first electrode formed on the substrate and a p-type absorber layer including a chalcogenide compound. An n-type layer includes a zinc oxysulfide material having a sulfur content adjusted to match a feature of the absorber layer. A transparent contact is formed on the n-type layer.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: TALIA S. GERSHON, OKI GUNAWAN, JEEHWAN KIM, YUN SEOG LEE
  • LIGHT EMITTING DIODE WITH ZnO EMITTER
    Publication number: 20170005229
    Abstract: A light emitting diode (LED) includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. A p-type confinement layer is provided on the p-type substrate. An emission layer is provided on the p-type confinement layer. An n-type confinement layer is provided on the emission layer. A transparent II-VI n-type contact layer is formed on the n-type confinement layer as a replacement for a current spreading layer, a III-V contact layer and an n-type ohmic contact.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Keith E. Fogel, Jeehwan Kim, Ning Li, Devendra K. Sadana
  • Solar cell made using a barrier layer between P-type and intrinsic layers
    Patent number: 9537038
    Abstract: A method for forming a photovoltaic device includes depositing a p-type layer on a substrate. A barrier layer is formed on the p-type layer by exposing the p-type layer to an oxidizing agent. An intrinsic layer is formed on the barrier layer, and an n-type layer is formed on the intrinsic layer.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: January 3, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, BAY ZU PRECISION CO., LTD
    Inventors: Tze-Chiang Chen, Augustin J. Hong, Chien-Chih Huang, Yu-Wei Huang, Jeehwan Kim, Devendra K. Sadana, Chih-Fu Tseng
  • MOSFET with ultra low drain leakage
    Patent number: 9536945
    Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: January 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Selective epitaxy using epitaxy-prevention layers
    Patent number: 9530643
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING
    Publication number: 20160358774
    Abstract: A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 8, 2016
    Inventors: Stephen W. Bedell, Joel P. De Souza, Jeehwan Kim, Devendra K. Sadana
  • CONTROLLABLE INDIUM DOPING FOR HIGH EFFICIENCY CZTS THIN-FILM SOLAR CELLS
    Publication number: 20160359070
    Abstract: A photovoltaic device includes a first contact layer formed on a substrate. An absorber layer includes Cu—Zn—Sn—S(Se) (CZTSSe) on the first contact layer. A buffer layer is formed in contact with the absorber layer. Metal dopants are dispersed in a junction region between the absorber layer and the buffer layer. The metal dopants have a valence between the absorber layer and the buffer layer to increase junction potential. A transparent conductive contact layer is formed over the buffer layer.
    Type: Application
    Filed: June 2, 2015
    Publication date: December 8, 2016
    Inventors: Talia S. Gershon, Jeehwan Kim, Yun Seog Lee, Teodor K. Todorov
  • SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING
    Publication number: 20160359023
    Abstract: A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 8, 2016
    Inventors: Stephen W. Bedell, Joel P. De Souza, Jeehwan Kim, Devendra K. Sadana