Patents by Inventor Jeehwan Kim

Jeehwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FINFET CMOS WITH Si NFET AND SiGe PFET
    Publication number: 20170170076
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin.
    Type: Application
    Filed: August 17, 2016
    Publication date: June 15, 2017
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim
  • Self-aligned source and drain regions for semiconductor devices
    Patent number: 9673290
    Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried L. Maurer, Devendra K. Sadana
  • Formation of large scale single crystalline graphene
    Patent number: 9666674
    Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: May 30, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Christos D. Dimitrakopoulos, Keith E. Fogel, Jeehwan Kim, Hongsik Park
  • Nanowires formed by employing solder nanodots
    Patent number: 9660116
    Abstract: A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: May 23, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana, Kuen-Ting Shiu
  • Junction interlayer dielectric for reducing leakage current in semiconductor devices
    Patent number: 9653570
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • Porous fin as compliant medium to form dislocation-free heteroepitaxial films
    Patent number: 9646832
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: May 9, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Reduced light degradation due to low power deposition of buffer layer
    Patent number: 9634164
    Abstract: Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a work function that falls substantially in a middle of a barrier formed between the transparent electrode and the p-type layer to provide a greater resistance to light induced degradation. An intrinsic layer and an n-type layer are formed over the p-type layer.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • REDUCTION OF DEFECT INDUCED LEAKAGE IN III-V SEMICONDUCTOR DEVICES
    Publication number: 20170110546
    Abstract: A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10 cm?2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Inventors: Joel P. de Souza, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • Doped zinc oxide and n-doping to reduce junction leakage
    Patent number: 9620592
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-doped layer is formed on the p-doped layer, the n-doped layer including a doped III-V material. A contact interface layer is formed on the n-doped layer. The contact interface layer includes a II-VI material. A contact metal is formed on the contact interface layer to form an electronic device.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Siegfried L. Maurer, Devendra K. Sadana
  • HETERO-INTEGRATION OF III-N MATERIAL ON SILICON
    Publication number: 20170092483
    Abstract: A hetero-integrated device includes a monocrystalline Si substrate and a trench formed in the substrate to expose a crystal surface at a bottom of the trench. Sidewall dielectric spacers are formed on sidewalls of the trench, and a III-V material layer is formed on the crystal surface at the bottom of the trench and is isolated from the sidewalls of the trench by the sidewall dielectric spacers.
    Type: Application
    Filed: December 13, 2016
    Publication date: March 30, 2017
    Inventors: Can Bayram, Christopher P. D'Emic, Devendra K. Sadana, Jeehwan Kim
  • High-z oxide nanoparticles embedded in semiconductor package
    Patent number: 9607952
    Abstract: A method includes embedding high-z oxide nanoparticles in a semiconductor package of a semiconductor packaged assembly, wherein the high-z nanoparticles are operative to emit electron radiation when exposed to a radiation source to render a semiconductor device in the semiconductor package inoperable.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Ying He, Jeehwan Kim, Ning Li
  • Hetero-integration of III-N material on silicon
    Patent number: 9601583
    Abstract: A hetero-integrated device includes a monocrystalline Si substrate and a trench formed in the substrate to expose a crystal surface at a bottom of the trench. Sidewall dielectric spacers are formed on sidewalls of the trench, and a III-V material layer is formed on the crystal surface at the bottom of the trench and is isolated from the sidewalls of the trench by the sidewall dielectric spacers.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: March 21, 2017
    Assignee: ARMONK BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Christopher P. D'Emic, Jeehwan Kim, Devendra K. Sadana
  • POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES
    Publication number: 20170076999
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 16, 2017
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES
    Publication number: 20170076998
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 16, 2017
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • BANDGAP GRADING OF CZTS SOLAR CELL
    Publication number: 20170077337
    Abstract: A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.
    Type: Application
    Filed: September 14, 2015
    Publication date: March 16, 2017
    Inventors: Talia S. Gershon, Marinus J.P. Hopstaken, Jeehwan Kim, Yun Seog Lee
  • Reduction of defect induced leakage in III-V semiconductor devices
    Patent number: 9583562
    Abstract: A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm?2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • SELECTIVE EPITAXY USING EPITAXY-PREVENTION LAYERS
    Publication number: 20170053796
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Application
    Filed: November 3, 2016
    Publication date: February 23, 2017
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Optoelectronics integration by transfer process
    Patent number: 9577196
    Abstract: A method for fabricating an optoelectronic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at the adhesion layer by mechanically yielding the adhesion layer. A conductive layer is applied to the material layer on a side opposite the release tape to form a transfer substrate. The transfer substrate is transferred to a target substrate to join the target substrate to the conductive layer of the transfer substrate. The release tape is removed from the material layer to form a top emission optoelectronic device.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Tze-bin Song
  • Gallium nitride material and device deposition on graphene terminated wafer and method of forming the same
    Patent number: 9574287
    Abstract: A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer. A layered stack of the metal containing monolayer and the epitaxial layer of gallium containing material is cleaved from the graphene layer that is present on the semiconductor and carbon containing substrate.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Can Bayram, Christos D. Dimitrakopoulos, Keith E. Fogel, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • LOW RESISTANCE CONTACT INTERLAYER FOR SEMICONDUCTOR DEVICES
    Publication number: 20170040463
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type material includes an oxide of a II-VI material. An oxygen scavenging interlayer is formed on the n-type material. An aluminum contact is formed in direct contact with the oxygen scavenging interlayer to form an electronic device.
    Type: Application
    Filed: August 7, 2015
    Publication date: February 9, 2017
    Inventors: Jeehwan Kim, Wencong Liu, Devendra K. Sadana