Patents by Inventor Jeehwan Kim

Jeehwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Double layered transparent conductive oxide for reduced schottky barrier in photovoltaic devices
    Patent number: 9917215
    Abstract: A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: March 13, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, BAY ZU PRECISION CO., LTD.
    Inventors: Shun-Ming Chen, Chien-Chih Huang, Joel P. Desouza, Augustin J. Hong, Jeehwan Kim, Chien-Yeh Ku, Devendra K. Sadana, Chuan-Wen Wang
  • Porous silicon relaxation medium for dislocation free CMOS devices
    Patent number: 9917021
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Self-aligned source and drain regions for semiconductor devices
    Patent number: 9916984
    Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried L. Maurer, Devendra K. Sadana
  • Photovoltaic device having layer with varying crystallinity
    Patent number: 9911888
    Abstract: A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Reduction of defect induced leakage in III-V semiconductor devices
    Patent number: 9905637
    Abstract: A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm?2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • MOSFET with ultra low drain leakage
    Patent number: 9887265
    Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Cone-shaped holes for high efficiency thin film solar cells
    Patent number: 9876129
    Abstract: A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: January 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Tunable semiconductor band gap reduction by strained sidewall passivation
    Patent number: 9865520
    Abstract: A semiconductor device includes a mesa structure having vertical sidewalls, the mesa structure including an active area comprising a portion of its height. A stressed passivation liner is formed on the vertical sidewalls of the mesa structure and over the portion of the active area. The stressed passivation liner induces strain in the active area to permit tuning of performance parameters of the mesa structure.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Christopher Heidelberger, Jeehwan Kim, Ning Li, Wencong Liu, Devendra K. Sadana
  • FinFET CMOS with Si NFET and SiGe PFET
    Patent number: 9865509
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim
  • WAFER BONDED SOLAR CELLS AND FABRICATION METHODS
    Publication number: 20180006180
    Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Inventors: STEPHEN W. BEDELL, CHENG-WEI CHENG, JEEHWAN KIM, DEVENDRA K. SADANA, KUEN-TING SHIU, NORMA E. SOSA CORTES
  • Apparatus and Methods for Electrical Switching
    Publication number: 20170365778
    Abstract: Electrical switching technologies employ the otherwise undesirable line defect in crystalline materials to form conductive filaments. A switching cell includes a crystalline layer disposed between an active electrode and another electrode. The crystalline layer has at least one channel, such as a line defect, extending from one surface of the crystalline layer to the other surface. Upon application of a voltage on the two electrodes, the active electrode provides metal ions that can migrate from the active electrode to the other electrode along the line defect, thereby forming a conductive filament. The switching cell can precisely locate the conductive filament within the line defect and increase the device-to-device switching uniformity.
    Type: Application
    Filed: December 22, 2016
    Publication date: December 21, 2017
    Inventors: Jeehwan Kim, Shinhyun Choi
  • SUBSTRATE-FREE THIN-FILM FLEXIBLE PHOTOVOLTAIC DEVICE AND FABRICATION METHOD
    Publication number: 20170358702
    Abstract: A method for thermal exfoliation includes providing a target layer on a substrate to form a structure. A stressor layer is deposited on the target layer. The structure is placed in a temperature controlled environment to induce differential thermal expansion between the target layer and the substrate. The target layer is exfoliated from the substrate when a critical temperature is achieved such that the target layer is separated from the substrate to produce a standalone, thin film device.
    Type: Application
    Filed: August 8, 2017
    Publication date: December 14, 2017
    Inventors: Oki Gunawan, Homare Hiroi, Jeehwan Kim, David B. Mitzi, Hiroki Sugimoto
  • Systems and Methods for Fabricating Single-Crystalline Diamond Membranes
    Publication number: 20170352538
    Abstract: A buffer layer is employed to fabricate diamond membranes and allow reuse of diamond substrates. In this approach, diamond membranes are fabricated on the buffer layer, which in turn is disposed on a diamond substrate that is lattice-matched to the diamond membrane. The weak bonding between the buffer layer and the diamond substrate allows ready release of the fabricated diamond membrane. The released diamond membrane is transferred to another substrate to fabricate diamond devices, while the diamond substrate is reused for another fabrication.
    Type: Application
    Filed: June 5, 2017
    Publication date: December 7, 2017
    Inventors: Jeehwan Kim, Dirk Robert ENGLUND, Mark A. HOLLIS, Travis WADE, Michael GEIS, Richard MOLNAR
  • Wafer bonded solar cells and fabrication methods
    Patent number: 9818901
    Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
  • LED light extraction enhancement enabled using self-assembled particles patterned surface
    Patent number: 9818909
    Abstract: A light emitting diode (LED) containing device including a light emitting diode (LED) structure, and a light transmissive substrate in contact with the LED structure. The light transmissive substrate has a texture surface tuned to include features with dimensions greater than a wavelength of light produced by the LED structure. In some embodiments, increasing the feature size of the texture to be comparable to the wavelength of light produced by the LED increases light extraction from the LED in comparison to when the feature size of the texture is substantially less or substantially larger than the wavelength of light.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Jeehwan Kim, Ning Li, Devendra K. Sadana
  • LEAKAGE-FREE IMPLANTATION-FREE ETSOI TRANSISTORS
    Publication number: 20170317171
    Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.
    Type: Application
    Filed: July 14, 2017
    Publication date: November 2, 2017
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Tandem solar cell with improved absorption material
    Patent number: 9806211
    Abstract: A photosensitive device and method includes a top cell having an N-type layer, a P-type layer and a top intrinsic layer therebetween. A bottom cell includes an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. The bottom intrinsic layer includes a Cu—Zn—Sn containing chalcogenide.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: October 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Oki Gunawan, Jeehwan Kim, David B. Mitzi, Devendra K. Sadana, Teodor K. Todorov
  • Substrate-free thin-film flexible photovoltaic device and fabrication method
    Patent number: 9799792
    Abstract: A method for thermal exfoliation includes providing a target layer on a substrate to form a structure. A stressor layer is deposited on the target layer. The structure is placed in a temperature controlled environment to induce differential thermal expansion between the target layer and the substrate. The target layer is exfoliated from the substrate when a critical temperature is achieved such that the target layer is separated from the substrate to produce a standalone, thin film device.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: October 24, 2017
    Assignees: International Business Machines Corporation, Solar Frontier K.K.
    Inventors: Oki Gunawan, Homare Hiroi, Jeehwan Kim, David B. Mitzi, Hiroki Sugimoto
  • Low resistance contact for semiconductor devices
    Patent number: 9799747
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type layer includes ZnO. An aluminum contact is formed in direct contact with the ZnO of the n-type material to form an electronic device.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • Self-aligned source and drain regions for semiconductor devices
    Patent number: 9786756
    Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried L. Maurer, Devendra K. Sadana