Abstract: A surgical system includes a plurality of voice sensors located in a surgical environment and configured to detect sound and generate a first plurality of signals. The surgical system also includes a position indicator, in proximity to a designated user, configured to indicate a first position of the designated user and generate a second signal representative of the first position. The surgical system further includes a processor configured to receive the first plurality of signals and the second signal and determine, based on the first plurality of signals, a second position. The processor is also configured to compare the detected sound with registered voice command of the designated user stored in a memory to verify the designated user's credentials, and send a command signal to a surgical instrument to carry out an operation related to the voice command based on at least one of the verification of the designated user's credentials, the first position and the second position.

Abstract: Formulations of 3-((3-(4-(2-(isobutylsulfonyl)phenoxy)-3-(trifluoromethyl)phenyl)-1,2,4-oxadiazol-5-yl)methyl)-5,5-dimethyl-1-(2-morpholinoethyl)imidazolidine-2,4-dione and pharmaceutically acceptable salts thereof, processes for their production, and uses thereof, including in the treatment of ocular diseases and disorders such as dry eye disease and Meibomian gland dysfunction (MGD).

Abstract: A new method for providing security in the context of transaction processing is disclosed. Machine learning is used to detect the potential for fraud and/or errors, select a payee account and payment rail, and initiate the processing of a payment. The method uses a trained payment method selection model to classify one or more of the candidate payment rails as optimal for transaction processing. The method also includes selecting a payee account that is associated with an identified payee and the selected payment rail, The system uses a payee account validation model to validate that the payee account will process on the selected payment rail. The system will then generate payment initialization data and transmit the data to an entity to originate the payment from the payer account to the selected payee account.

Abstract: Aspects of the present disclosure provide a method for fabricating a semiconductor device. For example, the method can include forming a first power rail, forming a first power input structure for coupling with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source, forming an active device between the first power rail and the first power input structure, and forming a first middle-of-line rail with a plurality of layers. The first middle-of-line rail can be configured to deliver the electrical power from the first power input structure to the first power rail. The first power rail can provide the electrical power to the active device for operation. Topmost and bottommost ones of the layers of the first middle-of-line rail can be as high as and leveled with top and bottom surfaces of the active device, respectively.

Abstract: An integrated monitoring panel for an elevator hoistway fire detection system is provided. The system includes a power supply, fault indicators for power and smoke detection, and alarm indicators for smoke and linear heat detection. The panel is configured to receive a terminus of a linear heat detection cable and a terminus of a smoke alarm detection piping. The panel includes a smoke detection test port that may receive simulated smoke and is connected to another terminus of the smoke alarm detection piping. A linear heat detection test switch triggers a test mode and interacts with the linear heat detection cable. During the test mode, the system circulates simulated smoke, analyzes air quality and electrical conditions, and activates corresponding alarm indicators. The performance of these functionalities helps determine whether the system meets operational criteria.

Abstract: A urinal assembly having a frame and a plurality of posts or posts extending from the frame. The frame can include a plurality of openings. The openings can be defined by a plurality of sides and corners. The posts can extend from the corners and/or from the sides of the openings. In some embodiments, posts extend from a first face and a second face of the frame.

Abstract: A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.

Abstract: A method for forming a semiconductor apparatus includes forming a plurality of repetitive initial structures over a substrate of the semiconductor apparatus. An initial structure in the plurality of repetitive initial structures is formed by forming a first stack of transistors along a Z direction substantially perpendicular to a substrate plane, and forming local interconnect structures. Each of the transistors in the first stack of transistors is sandwiched between two of the local interconnect structures. Vertical conductive structures are formed substantially parallel to the Z direction, a height of one of the vertical conductive structures along the Z direction being at least a height of the initial structure. The initial structure is functionalized into a final structure by forming one or more connections each electrically coupling one of the local interconnect structures to one of the vertical conductive structures.

Abstract: The present invention relates to a vertical-axis wind turbine device comprised of at least one housing with at least one vertical wall and a turbine with at least one base, at least one generator, and at least one blade. The housing is positioned around the turbine, wherein the vertical wall of the housing directs air from around the housing and into the curved blade of the turbine. This allows the turbine to gather air more efficiently and generate power more effectively.

Abstract: A semiconductor device includes a first device plane over a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed over the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.

Abstract: A urinal assembly having a frame and a plurality of posts or posts extending from the frame. The frame can include a plurality of openings. The openings can be defined by a plurality of sides and corners. The posts can extend from the corners and/or from the sides of the openings. In some embodiments, posts extend from a first face and a second face of the frame.

Abstract: A semiconductor device includes a device plane including an array of cells each including a transistor device. The device plane is formed on a working surface of a substrate and has a front side and a backside opposite the front side. A signal wiring structure is formed on the front side of the device plane. A front-side power distribution network (FSPDN) is positioned on the front side of the device plane. A buried power rail (BPR) is disposed below the device plane on the backside of the device plane. A power tap structure is formed in the device plane. The power tap structure electrically connects the BPR to the FSPDN and electrically connects the BPR to at least one of the transistor devices to provide power to the at least one of the transistor devices.

Abstract: A method of forming a semiconductor device includes forming, over a hardmask layer and an underlying layer of a substrate, a pattern of first trenches between adjacent template lines, each of the first trenches exposing a portion of the hardmask layer, and each of the template lines including a mandrel and spacers on sidewalls of the mandrel; forming a pattern of first blocks over the pattern of the first trenches and the template lines, the first blocks dividing the first trenches to form a pattern of first stencil trenches; transferring the pattern of first stencil trenches to the hardmask layer to form a pattern of first hardmask trenches, each of the first hardmask trenches exposing a portion of the underlying layer; forming a first fill layer filling the first hardmask trenches and exposing the mandrels; selectively removing the mandrels to form second trenches, each of the second trenches exposing a portion of the hardmask layer; and forming a conformal liner in the second trenches and over a surface of

Abstract: A semiconductor device includes a cell array having tracks and rows formed on a substrate. The tracks extend perpendicularly to the rows. A logic cell is formed across two adjacent rows within the cell array. The logic cell includes a cross-couple (XC) in each row and a plurality of poly tracks across the two adjacent rows. Each XC includes two cross-coupled complementary field-effect-transistors. Each poly track is configured to function as an inter-row gate for the XCs. A pair of signal tracks is positioned on opposing boundaries of the logic cell and electrically coupled to the plurality of poly tracks.

Abstract: A surgical tissue connector system for moving a first internal body tissue to a position away from a second internal body tissue and then holding the first internal body tissue in the position. Tissue connectors are secured to cords such that the length of cord between the tissue connectors can be easily adjusted in a laparoscopic work space.

Abstract: In a method of forming a semiconductor device, a plurality of transistor pairs is formed to be stacked over a substrate. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. A sequence of vertical and lateral etch steps are performed to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.

Abstract: A semiconductor device includes a field-effect transistor (FET) having a source/drain (S/D) structure and an interconnect structure in contact with the S/D structure. The interconnect structure has a barrier film at a surface of the interconnect structure separating the interconnect structure from materials surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S/ID structure. A second portion of the barrier film covers a second interface between the interconnect structure and dielectric materials adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier.