Patents by Inventor Jeffrey Smith

Jeffrey Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031287
    Abstract: In a method for processing a substrate, a conductive cap layer is selectively formed over a plurality of conductive structures that are positioned in a first dielectric layer. A second dielectric layer is selectively formed over the first dielectric layer. A third dielectric layer is selectively formed over the second dielectric layer. A fourth dielectric layer is then formed over the plurality of conductive structures and the third dielectric layer, and an interconnect structure is subsequently formed within the fourth dielectric layer. The interconnect structure includes a via structure that has a first portion positioned over the conductive cap layer so that sidewalls of the first portion are surrounded by the third dielectric layer, and a second portion disposed over the first portion and the third dielectric layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 8, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara Tapily, Jeffrey Smith
  • Publication number: 20210149956
    Abstract: A method for distributed pod-editing may be performed by an enhanced pod editor, and may include the following steps: receiving a framework for a pod, wherein the framework identifies one or more content items already assigned to one or more slots in the pod by one or more pod editors; determining attributes of the content items already assigned to the pod in a native taxonomy of the enhanced pod editor; determining restrictions on the pod's slots based on the attributes of the content items already assigned to the pod and on the pod's editorial constraints; rejecting content items already assigned to the pod that violate the restrictions on the pod's slots (if any); identifying candidate content items that comply with the restrictions on the pod's unfilled slots (if any), and selecting candidate content items and assigning the selected content items to the pod's unfilled slots
    Type: Application
    Filed: January 27, 2021
    Publication date: May 20, 2021
    Applicant: Xandr Inc.
    Inventors: Eric M. Hoffert, Alexander Krassel, Vikki Pitts, Radhika Shivapurkar, Michelle Smith, Jeffrey Weiss
  • Patent number: 11003703
    Abstract: Embodiments disclose a method for automatic summarization of content. The method includes accessing a plurality of stories from a plurality of data sources for a predefined time. Each story is associated with a media item. The method includes plotting the plurality of stories over the predefined time for determining one or more peaks and extracting a set of stories from the one or more peaks. The method includes detecting one or more themes from the set of stories using LDA algorithm. Each theme is associated with a group of stories. The method further includes determining at least one subset of stories for each theme from the group of stories representing the set of stories in the one or more peaks using RBM algorithm. The method includes generating a summarized content for each user based on an associated user profile and the at least one subset of stories.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 11, 2021
    Assignee: ZIGNAL LABS, INC.
    Inventors: Adam Beaugh, Andras Benke, Jay Buckingham, Jonathan R. Dodson, Jeffrey Fenchel, Loretta Jimenez, Michael Kramer, David Lineberger, Antonio Maldonado, Felix Medina Wong, Alex Smith, Fabien Vives
  • Patent number: 10995349
    Abstract: The present disclosure provides engineered proline hydroxylase polypeptides for the production of hydroxylated compounds, polynucleotides encoding the engineered proline hydroxylases, host cells capable of expressing the engineered proline hydroxylases, and methods of using the engineered proline hydroxylases to prepare compounds useful in the production of active pharmaceutical agents.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 4, 2021
    Assignee: Codexis, Inc.
    Inventors: Haibin Chen, Yong Koy Bong, Fabien L. Cabirol, Anupam Gohel Prafulchandra, Tao Li, Jeffrey C. Moore, Martina Quintanar-Audelo, Yang Hong, Steven J. Collier, Derek Smith
  • Patent number: 10995025
    Abstract: A liquid flow distribution system comprises a flow chamber and a rotor. The flow chamber has a flow chamber inlet, a flow chamber outlet and a chamber flow path extending from the flow chamber inlet to the flow chamber outlet. The flow chamber path is curved so as to generate a generally vortical flow in liquid passing through the chamber flow path. The rotor has a plurality of rotor blades rotatably mounted about a rotor axis. The rotor is mounted in proximity to the flow chamber outlet and positioned such that a flow of liquid exiting the flow chamber outlet impacts one or more of the rotor blades to rotationally drive the rotor. Rotational driving of the rotor in turn disperses liquid impacting the rotor blades.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: May 4, 2021
    Assignee: BIOGILL ENVIRONMENTAL PTY LIMITED
    Inventors: Mark John Smith, John David West, Jeremy Michael Wilson, Christopher Jeffrey Locker
  • Patent number: 10997572
    Abstract: A system and method for performing a financial transaction by determining a master account number associated with one or more accounts that a user may access, providing data to generate a user interface displaying a list of the accounts and an indicator associated with a financial transaction, receiving indicator information associating the indicator with one or more of the accounts, receiving terms for the financial transaction, and performing the financial transaction. The list of accounts may be expanded to view account information.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 4, 2021
    Assignee: CAPITAL ONE SERVICES, LLC
    Inventors: Elizabeth E. Cole, Julio Farach, Jill Sorg, Donald Jeffrey Smith, Hector Crespo, Lynn Jackson
  • Publication number: 20210122379
    Abstract: A control system for a vehicle using a forward-facing camera includes a look ahead module configured to determine a distance to a look ahead point. A lane center module determines a location of a lane center line. A vehicle center line module determines a location of a vehicle center line. A first lateral offset module determines a first lateral offset based on the look ahead point and the determined lane center line. A second lateral offset module determines a second lateral offset based on the determined lane center line and the vehicle center line. A yaw angle offset calculating module receives the first lateral offset, the second lateral offset and the distance to the look ahead point, calculates a yaw angle offset, and compensates a yaw angle error based on the yaw angle offset.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 29, 2021
    Inventors: Gabriel T. CHOI, Paul A. ADAM, Jeffrey S. PARKS, Lance A. SMITH
  • Patent number: 10991626
    Abstract: A semiconductor device includes: a substrate having a planar surface; a first gate-all-around field effect transistor (GAA-FET) provided on said substrate and comprising a first channel having an untrimmed volume of first channel material corresponding to a volume of the first channel material within a first stacked fin structure from which the first channel was formed; and a second GAA-FET provided on said substrate and comprising a second channel having a trimmed volume of second channel material which is less than said untrimmed volume of first channel material by a predetermined trim amount corresponding to a delay adjustment of the second GAA-FET relative to the first GAA-FET, wherein said first and second GAA FETs are electrically connected as complementary FETs.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 27, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Subhadeep Kal, Anton Devilliers
  • Publication number: 20210118798
    Abstract: A semiconductor device includes a first power rail, a first power input structure, a circuit and a first middle-of-line rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to connect with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source. The circuit is formed, on the substrate, by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers that form the circuit. The first middle-of-line rail is configured to deliver the electrical power from the first power input structure to the first power rail, and the first power rail provides the electrical power to the circuit for operation.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 22, 2021
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Lars LIEBMANN, Jeffrey SMITH, Anton DEVILLIERS, Daniel CHANEMOUGAME
  • Publication number: 20210118799
    Abstract: Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 22, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton deVilliers
  • Publication number: 20210114377
    Abstract: An example of a device (100) may include a valve body (108). The device may include a printing substance transfer window (122) through the valve body (108). The device (100) may include a printing substance dispensing nozzle (110) rotatable within the valve body (108) between a first orientation with an orifice of the printing substance dispensing nozzle (110) facing an internal face of the valve body (108) and a second orientation with the orifice (126) of the printing substance dispensing nozzle (110) facing the printing substance transfer window (122). The device (100) may include a dispensing-side gasket material (132) slideable against the internal face of the valve body (108) when rotating the printing substance dispensing nozzle (110) between the first orientation and the second orientation.
    Type: Application
    Filed: August 30, 2018
    Publication date: April 22, 2021
    Inventors: Jeffrey H. LUKE, Mathew LAVIGNE, Dean RICHTSMEIER, Kenneth SMITH, Sean Daniel FITZGERALD, Wesley R. SCHALK
  • Publication number: 20210098306
    Abstract: A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.
    Type: Application
    Filed: September 2, 2020
    Publication date: April 1, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Hiroaki Niimi, Jodi Grzeskowiak, Daniel Chanemougame, Lars Liebmann, Kandabara Tapily, Subhadeep Kal, Anton J. deVilliers
  • Publication number: 20210098294
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.
    Type: Application
    Filed: September 28, 2020
    Publication date: April 1, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey SMITH, Lars LIEBMANN, Daniel CHANEMOUGAME, Hiroki NIIMI, Kandabara TAPILY, Subhadeep KAL, Jodi GRZESKOWIAK, Anton DEVILLIERS
  • Patent number: 10964706
    Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey Smith, Anton J. deVilliers
  • Publication number: 20210088904
    Abstract: A method of forming a pattern on a substrate is provided. The method includes forming a first layer on an underlying layer of the substrate, where the first layer is patterned to have a first structure. The method also includes depositing a grafting material on side surfaces of the first structure, where the grafting material includes a solubility-shifting material. The method further includes diffusing the solubility-shifting material by a predetermined distance into a neighboring structure that abuts the solubility-shifting material, where the solubility-shifting material changes solubility of the neighboring structure in a developer, and removing soluble portions of the neighboring structure using the developer to form a second structure.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 25, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Anton J. DEVILLIERS, Jodi GRZESKOWIAK, Daniel FULFORD, Richard A. FARRELL, Jeffrey SMITH
  • Publication number: 20210082901
    Abstract: Techniques herein include methods for fabricating high density logic and memory for advanced circuit architecture. The methods can include forming multilayer stacks on separate substrates and forming bonding films over the multilayer stacks, then contacting and bonding the bonding films to form a combined structure including each of the multilayer stacks. The method can be repeated to form additional combinations. In between iterations, transistor devices may be formed from the combined structures. Ionized atom implantation can facilitate cleavage of a substrate destined for growth of additional multilayers, wherein an anneal weakens the substrate at a predetermined penetration depth of the ionized atom implantation.
    Type: Application
    Filed: April 21, 2020
    Publication date: March 18, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. GARDNER, H. Jim Fulford, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame
  • Publication number: 20210082750
    Abstract: A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 18, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Kai-Hung YU, Jodi GRZESKOWIAK, Nicholas JOY, Jeffrey SMITH
  • Patent number: D912794
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: March 9, 2021
    Assignee: Fresh Products, Inc.
    Inventors: Douglas S. Brown, Jeffrey A. Smith
  • Patent number: D914186
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 23, 2021
    Assignee: Fresh Products, Inc.
    Inventors: Douglas S. Brown, Jeffrey A. Smith
  • Patent number: D915786
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 13, 2021
    Assignee: Fresh Products, Inc.
    Inventors: Douglas S. Brown, Jeffrey A. Smith